FPGA chip on CPU board P014.49 V1.0 hardware driver header file. More...

#include "FPGA_Base.h"
#include "P014_47_V1_0_PFOTX.h"
#include "P014_48_V1_0_PFORX.h"
#include "P013_49_V1_0_RTD.h"
#include "P005_03_V2_0_AI.h"
#include "P014_42_V1_0_RIO.h"
#include "P005_06_V2_0_DIO.h"
#include "PWM_3P3L.h"

Include dependency graph for P014_49_V1_0_FPGA.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes
class	TFPGA
	FPGA hardware abstraction level class. More...

Macros
#define	IGBT_CONTROL_PORT_1_BASE_ADDRESS (0x60000040)

#define	IGBT_STATUS_PORT_1_BASE_ADDRESS (0x60000048)

#define	IGBT_CONTROL_PORT_2_BASE_ADDRESS (0x60000050)

#define	IGBT_STATUS_PORT_2_BASE_ADDRESS (0x60000058)

#define	IGBT_CONTROL_PORT_3_BASE_ADDRESS (0x60000060)

#define	IGBT_STATUS_PORT_3_BASE_ADDRESS (0x60000068)

#define	SENSOR_LINK_1_BASE_ADDRESS (0x60000070)

#define	SENSOR_LINK_2_BASE_ADDRESS (0x60000078)

#define	AI_BASE_ADDRESS (0x60000080)

#define	RTD_BASE_ADDRESS (0x60000010)

#define	RIO_BASE_ADDRESS (0x60000088)

#define	DIO_1_BASE_ADDRESS (0x60000020)

#define	DIO_2_BASE_ADDRESS (0x60000030)

#define	PWM_3P3L_BASE_ADDRESS (0x60000100)

#define	SENSOR_LINK_GRID_VOLTAGE_L12_BASE_ADDRESS (0x60000400)

#define	SENSOR_LINK_GRID_VOLTAGE_L23_BASE_ADDRESS (0x60000410)

#define	SENSOR_LINK_GRID_VOLTAGE_L31_BASE_ADDRESS (0x60000420)

#define	SENSOR_LINK_GSI_CURRENT_L1_BASE_ADDRESS (0x60000430)

#define	SENSOR_LINK_GSI_CURRENT_L2_BASE_ADDRESS (0x60000440)

#define	SENSOR_LINK_GSI_CURRENT_L3_BASE_ADDRESS (0x60000450)

#define	SENSOR_LINK_PV_INPUT_VOLTAGE_1_BASE_ADDRESS (0x60000460)

#define	SENSOR_LINK_PV_INPUT_VOLTAGE_2_BASE_ADDRESS (0x60000470)

#define	SENSOR_LINK_PV_INPUT_VOLTAGE_3_BASE_ADDRESS (0x60000480)

#define	SENSOR_LINK_PV_INPUT_CURRENT_1_BASE_ADDRESS (0x60000490)

#define	SENSOR_LINK_PV_INPUT_CURRENT_2_BASE_ADDRESS (0x600004A0)

#define	SENSOR_LINK_PV_INPUT_CURRENT_3_BASE_ADDRESS (0x600004B0)

#define	SENSOR_LINK_DC_BUS_VOLTAGE_TOP (0x600004C0)

#define	SENSOR_LINK_DC_BUS_VOLTAGE_BOTTOM (0x600004D0)

Functions
VOID	FPGA_Interrupt_Handler ()
	FPGA object interrupt handler. More...

Detailed Description

FPGA chip on CPU board P014.49 V1.0 hardware driver header file.

Attention: No special attention requered.

Copyright: (C) 2015-2020 ANVILEX LLC $HeadURL: https://192.168.3.4:8443/svn/P004_07/ConOpSys/Hardware/P014_49_V1_0_CB/P014_49_V1_0_FPGA.h $

Revision: 2262

Date: 2020-12-05 07:20:48 +0500 (Sa, 05 Dez 2020)

Author: minch

Macro Definition Documentation

◆ AI_BASE_ADDRESS

#define AI_BASE_ADDRESS (0x60000080)

◆ DIO_1_BASE_ADDRESS

#define DIO_1_BASE_ADDRESS (0x60000020)

◆ DIO_2_BASE_ADDRESS

#define DIO_2_BASE_ADDRESS (0x60000030)

◆ IGBT_CONTROL_PORT_1_BASE_ADDRESS

#define IGBT_CONTROL_PORT_1_BASE_ADDRESS (0x60000040)

◆ IGBT_CONTROL_PORT_2_BASE_ADDRESS

#define IGBT_CONTROL_PORT_2_BASE_ADDRESS (0x60000050)

◆ IGBT_CONTROL_PORT_3_BASE_ADDRESS

#define IGBT_CONTROL_PORT_3_BASE_ADDRESS (0x60000060)

◆ IGBT_STATUS_PORT_1_BASE_ADDRESS

#define IGBT_STATUS_PORT_1_BASE_ADDRESS (0x60000048)

◆ IGBT_STATUS_PORT_2_BASE_ADDRESS

#define IGBT_STATUS_PORT_2_BASE_ADDRESS (0x60000058)

◆ IGBT_STATUS_PORT_3_BASE_ADDRESS

#define IGBT_STATUS_PORT_3_BASE_ADDRESS (0x60000068)

◆ PWM_3P3L_BASE_ADDRESS

#define PWM_3P3L_BASE_ADDRESS (0x60000100)

◆ RIO_BASE_ADDRESS

#define RIO_BASE_ADDRESS (0x60000088)

◆ RTD_BASE_ADDRESS

#define RTD_BASE_ADDRESS (0x60000010)

◆ SENSOR_LINK_1_BASE_ADDRESS

#define SENSOR_LINK_1_BASE_ADDRESS (0x60000070)

◆ SENSOR_LINK_2_BASE_ADDRESS

#define SENSOR_LINK_2_BASE_ADDRESS (0x60000078)

◆ SENSOR_LINK_DC_BUS_VOLTAGE_BOTTOM

#define SENSOR_LINK_DC_BUS_VOLTAGE_BOTTOM (0x600004D0)

◆ SENSOR_LINK_DC_BUS_VOLTAGE_TOP

#define SENSOR_LINK_DC_BUS_VOLTAGE_TOP (0x600004C0)

◆ SENSOR_LINK_GRID_VOLTAGE_L12_BASE_ADDRESS

#define SENSOR_LINK_GRID_VOLTAGE_L12_BASE_ADDRESS (0x60000400)

◆ SENSOR_LINK_GRID_VOLTAGE_L23_BASE_ADDRESS

#define SENSOR_LINK_GRID_VOLTAGE_L23_BASE_ADDRESS (0x60000410)

◆ SENSOR_LINK_GRID_VOLTAGE_L31_BASE_ADDRESS

#define SENSOR_LINK_GRID_VOLTAGE_L31_BASE_ADDRESS (0x60000420)

◆ SENSOR_LINK_GSI_CURRENT_L1_BASE_ADDRESS

#define SENSOR_LINK_GSI_CURRENT_L1_BASE_ADDRESS (0x60000430)

◆ SENSOR_LINK_GSI_CURRENT_L2_BASE_ADDRESS

#define SENSOR_LINK_GSI_CURRENT_L2_BASE_ADDRESS (0x60000440)

◆ SENSOR_LINK_GSI_CURRENT_L3_BASE_ADDRESS

#define SENSOR_LINK_GSI_CURRENT_L3_BASE_ADDRESS (0x60000450)

◆ SENSOR_LINK_PV_INPUT_CURRENT_1_BASE_ADDRESS

#define SENSOR_LINK_PV_INPUT_CURRENT_1_BASE_ADDRESS (0x60000490)

◆ SENSOR_LINK_PV_INPUT_CURRENT_2_BASE_ADDRESS

#define SENSOR_LINK_PV_INPUT_CURRENT_2_BASE_ADDRESS (0x600004A0)

◆ SENSOR_LINK_PV_INPUT_CURRENT_3_BASE_ADDRESS

#define SENSOR_LINK_PV_INPUT_CURRENT_3_BASE_ADDRESS (0x600004B0)

◆ SENSOR_LINK_PV_INPUT_VOLTAGE_1_BASE_ADDRESS

#define SENSOR_LINK_PV_INPUT_VOLTAGE_1_BASE_ADDRESS (0x60000460)

◆ SENSOR_LINK_PV_INPUT_VOLTAGE_2_BASE_ADDRESS

#define SENSOR_LINK_PV_INPUT_VOLTAGE_2_BASE_ADDRESS (0x60000470)

◆ SENSOR_LINK_PV_INPUT_VOLTAGE_3_BASE_ADDRESS

#define SENSOR_LINK_PV_INPUT_VOLTAGE_3_BASE_ADDRESS (0x60000480)

Function Documentation

◆ FPGA_Interrupt_Handler()

VOID FPGA_Interrupt_Handler ( )

FPGA object interrupt handler.

Returns: None

Note: None

Classes

Macros

Functions