FPGA_Base.h

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//------------------------------------------------------------------------------
//! @file       FPGA_Base.h
//! @brief      FPGA chip base class header file.
//! @attention  No special attention requered.
//! @copyright  (C) 2015-2020 ANVILEX LLC
//!             $HeadURL: https://192.168.3.4:8443/svn/P004_07/ConOpSys/Peripherals/FPGA/FPGA_Base.h $
//!             $Revision: 2843 $
//!             $Date: 2021-08-06 16:39:48 +0500 (Fr, 06 Aug 2021) $
//!             $Author: ggavrituhin $
//------------------------------------------------------------------------------
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
//    this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of ANVILEX nor the names of its contributors may be
//    used to endorse or promote products derived from this software without
//    specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Protecting header files from mutual, recursive inclusion.
//------------------------------------------------------------------------------
 
#pragma once
 
//------------------------------------------------------------------------------
// Include standard libraries header files
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include thrid party header files
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include ConOpSys header files
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include ConOpSys application header files
//------------------------------------------------------------------------------
 
#include "Application_Task_Base.h"
 
//------------------------------------------------------------------------------
// Global defines
//------------------------------------------------------------------------------
 
// Physical size of FPGA address space in byte
#define FPGA_PHYSICAL_ADDRESS_SPACE_SIZE (0x10000)
 
//------------------------------------------------------------------------------
// Global macros
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Class declaration
//------------------------------------------------------------------------------
 
//! @brief FPGA base class
class TFPGA_Base
{
 
  //----------------------------------------------------------------------------
  // Public defines, methods and variables
  //----------------------------------------------------------------------------
 
  public:
 
    //--------------------------------------------------------------------------
    // Public defines
    //--------------------------------------------------------------------------
  
    //! @brief FPGA register models
    typedef union
    {
 
      // Register structure for generic access
      struct
      {
 
        //----------------------------------------------------------------------
        // Test registers
        //----------------------------------------------------------------------
 
        //! @brief Offset 0x00, FPGA access test register 1
        U16 u16_Test_Register_1;
 
        //! @brief Offset 0x01, FPGA access test register 2
        U16 u16_Test_Register_2;
 
        //! @brief Offset 0x02, FPGA access test register 3
        U16 u16_Test_Register_3;
 
        //! @brief Offset 0x03, FPGA access test register 4
        U16 u16_Test_Register_4;
 
        //----------------------------------------------------------------------
        // Information registers
        //----------------------------------------------------------------------
 
        //! @brief Offset 0x04, FPGA configuration ID register, low word
        U16 u16_FPGA_Configuration_ID_Low;
 
        //! @brief Offset 0x05, FPGA configuration ID register, high word
        U16 u16_FPGA_Configuration_ID_High;
 
        //! @brief Offset 0x06, FPGA version register
        U16 u16_FPGA_Version;
 
        //! @brief Offset 0x07, FPGA revision register
        U16 u16_FPGA_Revision;
 
        //! @brief Offset 0x08, FPGA clock frequency low word
        U16 u16_FPGA_Clock_Frequency_Low;
 
        //! @brief Offset 0x09, FPGA clock frequency high word
        U16 u16_FPGA_Clock_Frequency_High;
 
        //! @brief Offset 0x0A, FPGA slot size
        U16 u16_FPGA_Slot_Size;
 
        //! @brief Offset 0x0B, Reserve
        U16 u16_Reserve_0x0B;
 
        //! @brief Offset 0x0C, FPGA interrupt period register, low word
        U16 u16_FPGA_Interrupt_Period_Low;
 
        //! @brief Offset 0x0D, FPGA interrupt period register, low word
        U16 u16_FPGA_Interrupt_Period_High;
 
        //! @brief Offset 0x0E, FPGA watchdog period register
        U16 u16_FPGA_Watchdog_Period;
 
        //! @brief Offset 0x0F, FPGA watchdog control and status register
        U16 u16_Watchdog_CSR;
 
      } struct_Data;
 
      //! @brief Generic data registers
      U16 u16_Data[ FPGA_PHYSICAL_ADDRESS_SPACE_SIZE ];
 
    } TFPGA_Registers;
 
    //! @brief Register structure for generic unit ID access
    typedef struct
    {
 
      //! @brief 0x00 : Module identification low register
      U16 u16_Unit_ID_L;        
      
      //! @brief 0x01 : Module identification high register
      U16 u16_Unit_ID_H;        
 
    } TUnit_Registers;
 
    //--------------------------------------------------------------------------
    // Public methods
    //--------------------------------------------------------------------------
    
    //!-------------------------------------------------------------------------
    //! @brief     FPGA base class constructor method.
    //! @note      None
    //! \par       Override
    //!            Not allowed
    //! @attention Don't call this method directly.
    //--------------------------------------------------------------------------
 
    TFPGA_Base();
 
    //!-------------------------------------------------------------------------
    //! @brief     FPGA base class destructor method.
    //! @note      None
    //! \par       Override
    //!            Not allowed
    //! @attention Don't call this method directly.
    //--------------------------------------------------------------------------
 
    virtual ~TFPGA_Base();
 
    //!-------------------------------------------------------------------------
    //! @brief     FPGA interrupt method
    //! @note      None
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Interrupt();
 
    //!-------------------------------------------------------------------------
    //! @brief     FPGA object initialisation method.
    //! @note      None
    //! @param     [in] *struct_Registers_Base_Address - Pointer to registers base address
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Init( TFPGA_Registers *struct_Registers_Base_Address );
 
    BOOL Get_Internal_Slot_Module_ID( U8 u8_Slot_Index, U32 *u32_Module_ID );
 
    BOOL Get_External_Slot_Module_ID( U8 u8_Slot_Index, U32 *u32_Module_ID );
 
    //!-------------------------------------------------------------------------
    //! @brief     Increment test interconnect error counter method.
    //! @note      None
    //! @return    None
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Increment_Test_Interconnect_Error_Counter();
 
    //!-------------------------------------------------------------------------
    //! @brief     Check FPGA interconnection interface method.
    //! @note      None
    //! @return    None
    //! \par       Override
    //!            Optional
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Test_Interconnect_Interface();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA configuration ID method.
    //! @note      None
    //! @return    U32 - Return configurstion ID
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U32 Get_Configurstion_ID();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA configuration version method.
    //! @note      None
    //! @return    U16 - Return FPGA version
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U16 Get_Version();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA configuration revision method.
    //! @note      None
    //! @return    U16 - Return FPGA revision
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U16 Get_Revision();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA clock frequency in herz method.
    //! @note      None
    //! @return    U16 - Return FPGA clock frequency in herz
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U32 Get_Clock_Frequency();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA slot size method.
    //! @note      None
    //! @return    U16 - Return FPGA slot size
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U16 Get_Slot_Size();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA internal clock frequency in Hz  method.
    //! @note      None
    //! @return    F32 - Return Clock frequency
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    F32 Get_Clock_Frequency_In_Hz();
 
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA interconnect error count method.
    //! @note      None
    //! @return    U64 - FPGA interconnect error count
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U64 Get_Interconnect_Error_Count();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA interconnect test count method.
    //! @note      None
    //! @return    U64 - FPGA interconnect test count
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    U64 Get_Interconnect_Test_Count();
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA init status method.
    //! @note      None
    //! @return    BOOL - Return FPGA init status
    //! @retval    false - FPGA not installed
    //! @retval    true - FPGA installed
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    virtual BOOL Is_Installed();
 
    //!-------------------------------------------------------------------------
    //! @brief     Return FPGA configuration status method.
    //! @note      None
    //! @return    TRIL - Return FPGA init status
    //! @retval    false - FPFA not configured
    //! @retval    true - FPGA successful configured
    //! @retval    unset - FPGA did not start configured
    //! \par       Override
    //!            Not allowed
    //! @attention None
    //--------------------------------------------------------------------------
 
    TRIL Is_Configured();
 
    //!-------------------------------------------------------------------------
    //! @brief     Configure FPGA method.
    //! @note      None
    //! @return    BOOL - Return FPGA present status
    //! @retval    false - FPGA does not present
    //! @retval    true - FPGA present
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    virtual BOOL Configure() = 0;
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA PROG pin status method.
    //! @note      None
    //! @return    BOOL - Return FPGA PROG pin status
    //! @retval    false - FPGA PROG pin is low
    //! @retval    true - FPGA PROG pin is high
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    virtual BOOL FPGA_PROG_Pin_Status() = 0;
 
    //!-------------------------------------------------------------------------
    //! @brief     Get FPGA DONE pin status method.
    //! @note      None
    //! @return    BOOL - Return FPGA DONE pin status
    //! @retval    false - FPGA DONE pin is low
    //! @retval    true - FPGA DONE pin is high
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    virtual BOOL FPGA_DONE_Pin_Status() = 0;
 
    //!-------------------------------------------------------------------------
    //! @brief     Send general information about FPGA object
    //! @note      None
    //! @param     [in] *object_Protocol Pointer to the communication protocol object
    //! @return    None
    //! \par       Override
    //!            Optional
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Send_General_Information( TProtocol_Base *object_Protocol );
 
    //!-------------------------------------------------------------------------
    //! @brief     Send information about internal slots allocation
    //! @note      None
    //! @param     [in] *object_Protocol Pointer to the communication protocol object
    //! @return    None
    //! \par       Override
    //!            Optional
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Send_Internal_Slot_Information( TProtocol_Base *object_Protocol );
 
    //!-------------------------------------------------------------------------
    //! @brief     Send information about external slots allocation
    //! @note      None
    //! @param     [in] *object_Protocol Pointer to the communication protocol object
    //! @return    None
    //! \par       Override
    //!            Optional
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Send_External_Slot_Information( TProtocol_Base *object_Protocol );
 
    //!-------------------------------------------------------------------------
    //! @brief     Reset FPGA watchdog
    //! @note      None
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID Reset_Watchdog();
 
    BOOL Get_Slot_Module_Name_By_ID( U32 u32_Module_ID, C8 **c8_Module_Name );
 
    VOID Send_Internal_Module_Information( U8 u8_Slot, TProtocol_Base *object_Protocol );
    
    VOID Send_External_Module_Information( U8 u8_Slot, TProtocol_Base *object_Protocol );
 
  //----------------------------------------------------------------------------
  // Protected defines, methods and variables
  //----------------------------------------------------------------------------
 
  protected:
 
    //--------------------------------------------------------------------------
    // Protected methods
    //--------------------------------------------------------------------------
  
    //!-------------------------------------------------------------------------
    //! @brief     Write U16 value into FPGA using generic access.
    //! @note      None
    //! @param     [in] u16_Address - Logical address for read operation
    //! @param     [in] u16_Value - U16 value for write into FPGA
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID FPGA_Write_U16( U16 u16_Address, U16 u16_Value );
 
    //!-------------------------------------------------------------------------
    //! @brief     Read U16 value from FPGA using generic access.
    //! @note      None
    //! @param     [in] u16_Address - Logical address for read operation
    //! @param     [out] *u16_Value - Readed U16 value from FPGA
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    VOID FPGA_Read_U16( U16 u16_Address, U16 *u16_Value );
 
    //!-------------------------------------------------------------------------
    //! @brief     Enable FPGA interrupt method.
    //! @note      None
    //! @param     [in] u32_TickPriority - Priority
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    virtual VOID Interrupt_Enable( U32 u32_TickPriority ) = 0;
 
    //!-------------------------------------------------------------------------
    //! @brief     Disable FPGA interrupt method.
    //! @note      None
    //! @param     [in] u32_TickPriority - Priority
    //! @return    None
    //! \par       Override
    //!            Requered
    //! @attention None
    //--------------------------------------------------------------------------
 
    virtual VOID Interrupt_Disable() = 0;
 
    //--------------------------------------------------------------------------
    // Protected variables
    //--------------------------------------------------------------------------
    
    //! @brief Mapped FPGA registers
    volatile TFPGA_Registers *struct_Registers = (TFPGA_Registers*)NULL;
 
    //! @brief FPGA configuration status
    TRIL tril_FPGA_Configured = (TRIL)unset;
 
    //! @brief Interconnect test counter
    U64 u64_Test_Interconnect_Test_Counter = (U64)0;
 
    //! @brief Interconnect error counter for diagnose
    U64 u64_Test_Interconnect_Error_Counter = (U64)0;
 
    //! @brief Write pattern #1 for testng
    U16 u16_Write_Pattern_1;
 
    //! @brief Write pattern #2 for testng
    U16 u16_Write_Pattern_2;
 
    //! @brief Write pattern #3 for testng
    U16 u16_Write_Pattern_3;
 
    //! @brief Write pattern #4 for testng
    U16 u16_Write_Pattern_4;
 
    //! @brief Reading pattern #1 for testng
    U16 u16_Read_Pattern_1;
 
    //! @brief Reading pattern #2 for testng
    U16 u16_Read_Pattern_2;
 
    //! @brief Reading pattern #3 for testng
    U16 u16_Read_Pattern_3;
 
    //! @brief Reading pattern #4 for testng
    U16 u16_Read_Pattern_4;
 
    //! @brief Pointer to the application task
//    TApplication_Task_Base *object_Application_Task;
 
  //----------------------------------------------------------------------------
  // Private defines, methods and variables
  //----------------------------------------------------------------------------
 
  private:
 
    //--------------------------------------------------------------------------
    // Private defines
    //--------------------------------------------------------------------------
 
    //! @brief FPGA module descriptior structure
    typedef struct
    {
      
      //! @brief FPGA module identifier
      U16 u16_Module_ID;
      
      //! @brief FPGA module name
      C8* c8_Module_Name;
 
      //! @brief FPGA module description
      C8* c8_Module_Description;
 
    } TFPGA_Module_Descriptor;
 
    //--------------------------------------------------------------------------
    // Private variables
    //--------------------------------------------------------------------------
    
    //! @brief FPAG module descriptior database storage
    static const TFPGA_Module_Descriptor struct_FPGA_Module_Descriptor_Database[];
    
    //! @brief FPGA internal clock frequency in herz as integer value
    U32 u32_Clock_Frequency = (U32)50000000;
 
    //! @brief FPGA internal clock frequency in herz as float point value
    F32 f32_Clock_Frequency = (F32)50000000.0f;
 
};
 
//------------------------------------------------------------------------------
// End of file
//------------------------------------------------------------------------------