FPGA register models. More...
#include <FPGA_Base.h>
Public Attributes | |
| struct { | |
| U16 u16_Test_Register_1 | |
| Offset 0x00, FPGA access test register 1. More... | |
| U16 u16_Test_Register_2 | |
| Offset 0x01, FPGA access test register 2. More... | |
| U16 u16_Test_Register_3 | |
| Offset 0x02, FPGA access test register 3. More... | |
| U16 u16_Test_Register_4 | |
| Offset 0x03, FPGA access test register 4. More... | |
| U16 u16_FPGA_Configuration_ID_Low | |
| Offset 0x04, FPGA configuration ID register, low word. More... | |
| U16 u16_FPGA_Configuration_ID_High | |
| Offset 0x05, FPGA configuration ID register, high word. More... | |
| U16 u16_FPGA_Version | |
| Offset 0x06, FPGA version register. More... | |
| U16 u16_FPGA_Revision | |
| Offset 0x07, FPGA revision register. More... | |
| U16 u16_FPGA_Clock_Frequency_Low | |
| Offset 0x08, FPGA clock frequency low word. More... | |
| U16 u16_FPGA_Clock_Frequency_High | |
| Offset 0x09, FPGA clock frequency high word. More... | |
| U16 u16_FPGA_Slot_Size | |
| Offset 0x0A, FPGA slot size. More... | |
| U16 u16_Reserve_0x0B | |
| Offset 0x0B, Reserve. More... | |
| U16 u16_FPGA_Interrupt_Period_Low | |
| Offset 0x0C, FPGA interrupt period register, low word. More... | |
| U16 u16_FPGA_Interrupt_Period_High | |
| Offset 0x0D, FPGA interrupt period register, low word. More... | |
| U16 u16_FPGA_Watchdog_Period | |
| Offset 0x0E, FPGA watchdog period register. More... | |
| U16 u16_Watchdog_CSR | |
| Offset 0x0F, FPGA watchdog control and status register. More... | |
| } | struct_Data |
| U16 | u16_Data [FPGA_PHYSICAL_ADDRESS_SPACE_SIZE] |
| Generic data registers. More... | |
Detailed Description
FPGA register models.
Member Data Documentation
◆
| struct { ... } TFPGA_Base::TFPGA_Registers::struct_Data |
◆ u16_Data
| U16 TFPGA_Base::TFPGA_Registers::u16_Data[FPGA_PHYSICAL_ADDRESS_SPACE_SIZE] |
Generic data registers.
Referenced by TFPGA_Base::FPGA_Read_U16(), TFPGA_Base::FPGA_Write_U16(), TFPGA::Read_U16(), and TFPGA::Write_U16().
◆ u16_FPGA_Clock_Frequency_High
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Clock_Frequency_High |
Offset 0x09, FPGA clock frequency high word.
Referenced by TFPGA_Base::Get_Clock_Frequency().
◆ u16_FPGA_Clock_Frequency_Low
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Clock_Frequency_Low |
Offset 0x08, FPGA clock frequency low word.
Referenced by TFPGA_Base::Get_Clock_Frequency().
◆ u16_FPGA_Configuration_ID_High
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Configuration_ID_High |
Offset 0x05, FPGA configuration ID register, high word.
Referenced by TFPGA_Base::Get_Configurstion_ID().
◆ u16_FPGA_Configuration_ID_Low
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Configuration_ID_Low |
Offset 0x04, FPGA configuration ID register, low word.
Referenced by TFPGA_Base::Get_Configurstion_ID().
◆ u16_FPGA_Interrupt_Period_High
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Interrupt_Period_High |
Offset 0x0D, FPGA interrupt period register, low word.
◆ u16_FPGA_Interrupt_Period_Low
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Interrupt_Period_Low |
Offset 0x0C, FPGA interrupt period register, low word.
◆ u16_FPGA_Revision
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Revision |
Offset 0x07, FPGA revision register.
Referenced by TFPGA_Base::Get_Revision().
◆ u16_FPGA_Slot_Size
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Slot_Size |
Offset 0x0A, FPGA slot size.
Referenced by TFPGA_Base::Get_Slot_Size().
◆ u16_FPGA_Version
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Version |
Offset 0x06, FPGA version register.
Referenced by TFPGA_Base::Get_Version().
◆ u16_FPGA_Watchdog_Period
| U16 TFPGA_Base::TFPGA_Registers::u16_FPGA_Watchdog_Period |
Offset 0x0E, FPGA watchdog period register.
◆ u16_Reserve_0x0B
| U16 TFPGA_Base::TFPGA_Registers::u16_Reserve_0x0B |
Offset 0x0B, Reserve.
◆ u16_Test_Register_1
| U16 TFPGA_Base::TFPGA_Registers::u16_Test_Register_1 |
Offset 0x00, FPGA access test register 1.
Referenced by TFPGA::Test_Interconnect_Interface(), and TFPGA_Base::Test_Interconnect_Interface().
◆ u16_Test_Register_2
| U16 TFPGA_Base::TFPGA_Registers::u16_Test_Register_2 |
Offset 0x01, FPGA access test register 2.
Referenced by TFPGA::Test_Interconnect_Interface(), and TFPGA_Base::Test_Interconnect_Interface().
◆ u16_Test_Register_3
| U16 TFPGA_Base::TFPGA_Registers::u16_Test_Register_3 |
Offset 0x02, FPGA access test register 3.
Referenced by TFPGA::Test_Interconnect_Interface(), and TFPGA_Base::Test_Interconnect_Interface().
◆ u16_Test_Register_4
| U16 TFPGA_Base::TFPGA_Registers::u16_Test_Register_4 |
Offset 0x03, FPGA access test register 4.
Referenced by TFPGA::Test_Interconnect_Interface(), and TFPGA_Base::Test_Interconnect_Interface().
◆ u16_Watchdog_CSR
| U16 TFPGA_Base::TFPGA_Registers::u16_Watchdog_CSR |
Offset 0x0F, FPGA watchdog control and status register.
Referenced by TFPGA_Base::Reset_Watchdog().
The documentation for this union was generated from the following file:
- ConOpSys/Peripherals/FPGA/FPGA_Base.h
