P014_49_V1_0_FPGA.h

Go to the documentation of this file.

//------------------------------------------------------------------------------
//! @file       P014_49_V1_0_FPGA.h
//! @brief      FPGA chip on CPU board P014.49 V1.0 hardware driver header file.
//! @attention  No special attention requered.
//! @copyright  (C) 2015-2020 ANVILEX LLC
//!             $HeadURL: https://192.168.3.4:8443/svn/P004_07/ConOpSys/Hardware/P014_49_V1_0_CB/P014_49_V1_0_FPGA.h $
//!             $Revision: 2262 $
//!             $Date: 2020-12-05 07:20:48 +0500 (Sa, 05 Dez 2020) $
//!             $Author: minch $
//------------------------------------------------------------------------------
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
//    this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of ANVILEX nor the names of its contributors may be
//    used to endorse or promote products derived from this software without
//    specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Protecting header files from mutual, recursive inclusion.
//------------------------------------------------------------------------------
 
#pragma once
 
//------------------------------------------------------------------------------
// Include standard libraries header files
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include thrid party header files
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include ConOpSys header files
//------------------------------------------------------------------------------
 
#include "FPGA_Base.h"
#include "P014_47_V1_0_PFOTX.h"
#include "P014_48_V1_0_PFORX.h"
#include "P013_49_V1_0_RTD.h"
#include "P005_03_V2_0_AI.h"
#include "P014_42_V1_0_RIO.h"
#include "P005_06_V2_0_DIO.h"
#include "PWM_3P3L.h"
 
//------------------------------------------------------------------------------
// Include ConOpSys application header files
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Macros
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// FPGA base address
//------------------------------------------------------------------------------
  
#define IGBT_CONTROL_PORT_1_BASE_ADDRESS (0x60000040)
#define IGBT_STATUS_PORT_1_BASE_ADDRESS  (0x60000048)
#define IGBT_CONTROL_PORT_2_BASE_ADDRESS (0x60000050)
#define IGBT_STATUS_PORT_2_BASE_ADDRESS  (0x60000058)
#define IGBT_CONTROL_PORT_3_BASE_ADDRESS (0x60000060)
#define IGBT_STATUS_PORT_3_BASE_ADDRESS  (0x60000068)
 
#define SENSOR_LINK_1_BASE_ADDRESS       (0x60000070)
#define SENSOR_LINK_2_BASE_ADDRESS       (0x60000078)
 
#define AI_BASE_ADDRESS                  (0x60000080)
 
#define RTD_BASE_ADDRESS                 (0x60000010)
 
#define RIO_BASE_ADDRESS                 (0x60000088)
 
#define DIO_1_BASE_ADDRESS               (0x60000020)
#define DIO_2_BASE_ADDRESS               (0x60000030)
 
 
#define PWM_3P3L_BASE_ADDRESS                         (0x60000100)
 
#define SENSOR_LINK_GRID_VOLTAGE_L12_BASE_ADDRESS     (0x60000400)
#define SENSOR_LINK_GRID_VOLTAGE_L23_BASE_ADDRESS     (0x60000410)
#define SENSOR_LINK_GRID_VOLTAGE_L31_BASE_ADDRESS     (0x60000420)
 
#define SENSOR_LINK_GSI_CURRENT_L1_BASE_ADDRESS       (0x60000430)
#define SENSOR_LINK_GSI_CURRENT_L2_BASE_ADDRESS       (0x60000440)
#define SENSOR_LINK_GSI_CURRENT_L3_BASE_ADDRESS       (0x60000450)
 
#define SENSOR_LINK_PV_INPUT_VOLTAGE_1_BASE_ADDRESS   (0x60000460)
#define SENSOR_LINK_PV_INPUT_VOLTAGE_2_BASE_ADDRESS   (0x60000470)
#define SENSOR_LINK_PV_INPUT_VOLTAGE_3_BASE_ADDRESS   (0x60000480)
 
#define SENSOR_LINK_PV_INPUT_CURRENT_1_BASE_ADDRESS   (0x60000490)
#define SENSOR_LINK_PV_INPUT_CURRENT_2_BASE_ADDRESS   (0x600004A0)
#define SENSOR_LINK_PV_INPUT_CURRENT_3_BASE_ADDRESS   (0x600004B0)
 
#define SENSOR_LINK_DC_BUS_VOLTAGE_TOP                (0x600004C0)
#define SENSOR_LINK_DC_BUS_VOLTAGE_BOTTOM             (0x600004D0)
 
//------------------------------------------------------------------------------
//! @brief FPGA hardware abstraction level class
//------------------------------------------------------------------------------
 
class TFPGA : public TFPGA_Base
{
  
  //----------------------------------------------------------------------------
  // Public defines, methods and variables
  //----------------------------------------------------------------------------
 
  public:
 
    // Constructor and destructor
    TFPGA();
    ~TFPGA();
    
    // Initialization and finalization methods
    VOID Init();
    VOID Done();
    
    // Configuration control
    virtual VOID Configure();
 
    // Interrupt management methods
    virtual VOID Interrupt_Enable( U32 u32_TickPriority );
    virtual VOID Interrupt_Disable();
    
    // Register access methods
    virtual VOID Write_U16( U16 u16_Address, U16 u16_Value );
    virtual VOID Read_U16( U16 u16_Address, U16 *u16_Value );
 
    VOID Test_Interconnect_Interface();
    
    //--------------------------------------------------------------------------
    // Public objects
    //--------------------------------------------------------------------------
 
    // FPGA units   
    TP014_47_V1_0_PFOTX object_IGBT_Control_Port_1;
    TP014_48_V1_0_PFORX object_IGBT_Status_Port_1;
    TP014_47_V1_0_PFOTX object_IGBT_Control_Port_2;
    TP014_48_V1_0_PFORX object_IGBT_Status_Port_2;
    TP014_47_V1_0_PFOTX object_IGBT_Control_Port_3;
    TP014_48_V1_0_PFORX object_IGBT_Status_Port_3;
    TP014_48_V1_0_PFORX object_Sensor_Link_1;
    TP014_48_V1_0_PFORX object_Sensor_Link_2;
    TP005_03_V2_0_AI object_AI;
    TP013_49_V1_0_RTD object_RTD;
    TP014_42_V1_0_RIO object_RIO;
    TP005_06_V2_0_DIO object_DIO_1;
    TP005_06_V2_0_DIO object_DIO_2;
    
    TPWM_3P3L object_PWM_3P3L;
 
    U32 u32_Test_Interconnect_Error_Counter;
 
  //----------------------------------------------------------------------------
  // Protected defines, methods and variables
  //----------------------------------------------------------------------------
 
  protected:
    
  //----------------------------------------------------------------------------
  // Private defines, methods and variables
  //----------------------------------------------------------------------------
  
  private:
    
};
 
//------------------------------------------------------------------------------
// Export references to the objects
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Export references to the functions
//------------------------------------------------------------------------------
 
extern VOID FPGA_Interrupt_Handler();
 
//------------------------------------------------------------------------------
// End Of File
//------------------------------------------------------------------------------