11 #if __ARMCC_VERSION >= 6000000
12 __asm(
".global __use_no_semihosting");
13 #elif __ARMCC_VERSION >= 5000000
14 #pragma import(__use_no_semihosting)
16 #error Unsupported compiler
29 #define HARDWARE_VERSION ( (C8*)"P017.39 V1" )
30 #define HARDWARE_ID ( (U32)3 )
119 #define SPI2_MODULE_INSTALLED (true)
142 #ifndef ADC_MODULE_INSTALLED
149 #error ERROR: Undefined compilation switch: ADC_MODULE_INSTALLED
163 #ifndef DAC_MODULE_INSTALLED
170 #error "ERROR: Undefined compilation switch: DAC_MODULE_INSTALLED"
184 #ifndef DIO_MODULE_INSTALLED
191 #error "ERROR: Undefined compilation switch: DIO_MODULE_INSTALLED"
205 #ifndef FPGA_MODULE_INSTALLED
212 #error ERROR: Undefined compilation switch: FPGA_MODULE_INSTALLED
227 #if ( FPGA_MODULE_INSTALLED == (true) )
234 #define FPGA_BASE ((U32)0x60000000)
242 #define FPGA_ADDRESS_SLOT_SIZE (0x40)
245 #define FPGA_BACKPLANE_SLOT_AREA_OFFSET (U32)0x00001000
248 #define FPGA_INTERNAL_SLOT_AREA_OFFSET (U32)0x00000000
252 #define FPGA_BACKPLANE_SLOT_1 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 0 * FPGA_ADDRESS_SLOT_SIZE ) )
253 #define FPGA_BACKPLANE_SLOT_2 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 1 * FPGA_ADDRESS_SLOT_SIZE ) )
254 #define FPGA_BACKPLANE_SLOT_3 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 2 * FPGA_ADDRESS_SLOT_SIZE ) )
255 #define FPGA_BACKPLANE_SLOT_4 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 3 * FPGA_ADDRESS_SLOT_SIZE ) )
256 #define FPGA_BACKPLANE_SLOT_5 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 4 * FPGA_ADDRESS_SLOT_SIZE ) )
257 #define FPGA_BACKPLANE_SLOT_6 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 5 * FPGA_ADDRESS_SLOT_SIZE ) )
258 #define FPGA_BACKPLANE_SLOT_7 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 6 * FPGA_ADDRESS_SLOT_SIZE ) )
259 #define FPGA_BACKPLANE_SLOT_8 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 7 * FPGA_ADDRESS_SLOT_SIZE ) )
260 #define FPGA_BACKPLANE_SLOT_9 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 8 * FPGA_ADDRESS_SLOT_SIZE ) )
261 #define FPGA_BACKPLANE_SLOT_10 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 9 * FPGA_ADDRESS_SLOT_SIZE ) )
262 #define FPGA_BACKPLANE_SLOT_11 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 10 * FPGA_ADDRESS_SLOT_SIZE ) )
263 #define FPGA_BACKPLANE_SLOT_12 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 11 * FPGA_ADDRESS_SLOT_SIZE ) )
264 #define FPGA_BACKPLANE_SLOT_13 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 12 * FPGA_ADDRESS_SLOT_SIZE ) )
265 #define FPGA_BACKPLANE_SLOT_14 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 13 * FPGA_ADDRESS_SLOT_SIZE ) )
266 #define FPGA_BACKPLANE_SLOT_15 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 14 * FPGA_ADDRESS_SLOT_SIZE ) )
267 #define FPGA_BACKPLANE_SLOT_16 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 15 * FPGA_ADDRESS_SLOT_SIZE ) )
269 #define FPGA_INTERNAL_SLOT_1 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 0 * FPGA_ADDRESS_SLOT_SIZE ) )
270 #define FPGA_INTERNAL_SLOT_2 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 1 * FPGA_ADDRESS_SLOT_SIZE ) )
271 #define FPGA_INTERNAL_SLOT_3 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 2 * FPGA_ADDRESS_SLOT_SIZE ) )
272 #define FPGA_INTERNAL_SLOT_4 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 3 * FPGA_ADDRESS_SLOT_SIZE ) )
273 #define FPGA_INTERNAL_SLOT_5 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 4 * FPGA_ADDRESS_SLOT_SIZE ) )
274 #define FPGA_INTERNAL_SLOT_6 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 5 * FPGA_ADDRESS_SLOT_SIZE ) )
275 #define FPGA_INTERNAL_SLOT_7 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 6 * FPGA_ADDRESS_SLOT_SIZE ) )
276 #define FPGA_INTERNAL_SLOT_8 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 7 * FPGA_ADDRESS_SLOT_SIZE ) )
277 #define FPGA_INTERNAL_SLOT_9 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 8 * FPGA_ADDRESS_SLOT_SIZE ) )
278 #define FPGA_INTERNAL_SLOT_10 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 9 * FPGA_ADDRESS_SLOT_SIZE ) )
279 #define FPGA_INTERNAL_SLOT_11 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 10 * FPGA_ADDRESS_SLOT_SIZE ) )
280 #define FPGA_INTERNAL_SLOT_12 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 11 * FPGA_ADDRESS_SLOT_SIZE ) )
281 #define FPGA_INTERNAL_SLOT_13 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 12 * FPGA_ADDRESS_SLOT_SIZE ) )
282 #define FPGA_INTERNAL_SLOT_14 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 13 * FPGA_ADDRESS_SLOT_SIZE ) )
283 #define FPGA_INTERNAL_SLOT_15 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 14 * FPGA_ADDRESS_SLOT_SIZE ) )
284 #define FPGA_INTERNAL_SLOT_16 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 15 * FPGA_ADDRESS_SLOT_SIZE ) )
294 #ifndef COM1_COMMUNICATION_MODE
301 #error ERROR: Undefined compilation switch: COM1_COMMUNICATION_MODE
311 extern TCOM0 object_System_COM0;
313 #if ( COM1_COMMUNICATION_MODE == (true) )
331 #ifndef COM1_COMMUNICATION_MODE
338 #error "ERROR: Undefined compilation switch: COM1_COMMUNICATION_MODE"
350 extern "C" VOID System_UART1_Interrupt_Handler();
352 #if ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_NONE )
363 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX )
374 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_V2 )
385 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_MASTER )
396 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_RTU )
407 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_ASCII )
417 #error "ERROR: MODBUS ASCII communication mode not implemented for COM1."
426 #error "ERROR: Undefined or unknown communication mode for COM1."
436 #ifndef COM2_COMMUNICATION_MODE
443 #error "ERROR: Undefined compilation switch: COM2_COMMUNICATION_MODE"
455 extern "C" VOID System_UART6_Interrupt_Handler();
457 #if ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_NONE )
466 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX )
475 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_V2 )
484 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_MASTER )
493 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_RTU )
502 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_ASCII )
512 #error "ERROR: MODBUS ASCII communication mode not implemented for COM2."
521 #error "ERROR: Undefined or unknown communication mode for COM2."
531 #ifndef COM3_COMMUNICATION_MODE
538 #error "ERROR: Undefined compilation switch: COM3_COMMUNICATION_MODE"
550 extern "C" VOID System_COM3_Interrupt_Handler();
552 #if ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_NONE )
561 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX )
570 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_RTU )
579 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_ASCII )
589 #error "ERROR: MODBUS ASCII communication mode not implemented for COM3."
591 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_SIMCOM )
601 #error "ERROR: SIMCOM communication mode not implemented for COM3."
610 #error "ERROR: Undefined or unknown communication mode for COM3."
620 #ifndef ETHERNET_MODULE_INSTALLED
627 #error "ERROR: Undefined compilation switch: ETHERNET_MODULE_INSTALLED"
639 extern "C" VOID System_ETH_Interrupt_Handler();
641 #if ( ETHERNET_MODULE_INSTALLED == true )
665 #ifndef CAN1_MODULE_INSTALLED
672 #error "ERROR: Undefined compilation switch: CAN1_MODULE_INSTALLED"
687 extern "C" VOID System_CAN1_RX0_Interrupt_Handler();
688 extern "C" VOID System_CAN1_RX1_Interrupt_Handler();
689 extern "C" VOID System_CAN1_TX_Interrupt_Handler();
690 extern "C" VOID System_CAN1_SCE_Interrupt_Handler();
691 extern "C" VOID System_CAN2_RX0_Interrupt_Handler();
692 extern "C" VOID System_CAN2_RX1_Interrupt_Handler();
693 extern "C" VOID System_CAN2_TX_Interrupt_Handler();
694 extern "C" VOID System_CAN2_SCE_Interrupt_Handler();
696 #if ( CAN1_MODULE_INSTALLED == (true) )
723 #ifndef ADDISIONAL_MODULE_COMMUNICATION
730 #error "ERROR: Undefined compilation switch: ADDISIONAL_MODULE_COMMUNICATION"
739 #if ( ADDISIONAL_MODULE_COMMUNICATION == PB_DPV_1 )
796 #ifndef COMMAND_MANAGER_MODULE_INSTALLED
803 #error "ERROR: Undefined compilation switch: COMMAND_MANAGER_MODULE_INSTALLED"
812 #if ( COMMAND_MANAGER_MODULE_INSTALLED == (true) )
831 #ifndef EVENT_MANAGER_MODULE_INSTALLED
838 #error ERROR: Undefined compilation switch: EVENT_MANAGER_MODULE_INSTALLED
847 #if ( EVENT_MANAGER_MODULE_INSTALLED == (true) )
855 #define EVENT_DATABASE_STORAGE_INSTALLED (true)
859 extern TS25FL512 *object_Event_Database_Storage;
874 #ifndef SCOPE_MODULE_INSTALLED
881 #error "ERROR: Undefined compilation switch: SCOPE_MODULE_INSTALLED"
890 #if ( SCOPE_MODULE_INSTALLED == (true) )
ANYBUS module base class header file.
ANYBUS Profibus module driver class header file.
STM32F429 on-chip CAN1 class header file.
STM32F429 on-chip CAN2 class for P017_39_KG3_CB header file.
STM32F429 CPU class header file.
ConOpSys command manager class header file.
void VOID
Datatypesess datatype definition.
Definition: Defines.h:105
System ETHERNET communication link unit.
Event manager class header file.
NVRAM chip FM25V02 hardware driver class header file.
FPGA driver calss header file for P017_39_KG3_CB.
Function block manager class header file.
STM32F429 heap class header file.
P017.39 control board LED class header file.
STM32F429 on-chip NVIC module class header file.
VOID FPGA_Interrupt_Handler()
Definition: P013_35_V1_3_CPU.cpp:117
ConOpSys parameter database manager class header file.
Communication protocol ANVILEX master over UART class header file.
Communication protocol ANVILEX over UART class header file.
Communication protocol ANVILEX over UART class header file.
Communication protocol CANopen over CAN class header file.
Communication protocol IP over Ethernet class header file.
Communication protocol MODBUS RTU over UART class header file.
Dummy communication protocol over UART class header file.
STM32F429 on-chip RTC module class header file.
SPI NAND FLASH memory chip S25FL512 hardware driver class header file.
STM32F429 SPI2 master class header file.
STM32F429 SPI4 master class header file.
STM32F429 SPI5 master class header file.
STM32F429 stack class header file.
STM32F429 on-chip SYSTICK timer module class header file.
Signal recorder class header file.
Virtual communication link COM0 class header file.
TABCC_DPV1 object_ABCC
ABCC global object instance.
Definition: System_Resource.cpp:1452
TProtocol_PLUG_Over_UART object_Protocol_Over_COM0
Definition: System_Resource.cpp:1177
TProtocol_CANopen_Slave_Over_CAN object_Protocol_Over_CAN
CANopen slave protocol over CAN global object instance.
Definition: System_Resource.cpp:1438
TCommand_Manager object_Command_Manager
Command manager global object instance.
Definition: System_Resource.cpp:1464
TProtocol_IP_Over_ETHERNET object_Protocol_Over_ETHERNET
IP protocol over ETHERNET global object instance.
Definition: System_Resource.cpp:1427
STM32F429 on-chip TIMER2 module class header file.
System UART communication link unit.
System UART communication link unit.
System UART communication link unit.
STM32F429 on-chip WTD module class header file.
Definition: ABCC_DPV1.h:111
STM32F429 on-chip CAN1 hardware abstraction layer class for P017_39_KG3_CB.
Definition: CAN1_P017_39_KG3_CB.h:70
STM32F429 on-chip CAN2 hardware abstraction layer class for P017_39_KG3_CB.
Definition: CAN2_P017_39_KG3_CB.h:71
Virtual communication link COM0 class.
Definition: System_COM0.h:91
STM32F429 CPU hardware class.
Definition: CPU_STM32F429.h:69
ConOpSys terminal command manager class.
Definition: Command_Manager.h:86
STM32F429 on-chip Ethernet hardware abstraction layer class for P017_39_CB.
Definition: ETHERNET_P017_39_CB.h:95
Event manager class.
Definition: Event_Manager.h:70
FPGA hardware dependent driver class for P017_39_KG3_CB.
Definition: FPGA_P017_39_KG3_CB.h:75
STM32F429 heap class.
Definition: HEAP_STM32F429.h:63
P017.39 control board system LED class.
Definition: LED_P017_39_KG3_CB.h:57
Communication protocol ANVILEX master over UART class.
Definition: Protocol_ANVILEX_Master_Over_UART.h:62
Communication protocol ANVILEX over UART class.
Definition: Protocol_ANVILEX_Over_UART_V2.h:62
Communication protocol ANVILEX over UART class.
Definition: Protocol_ANVILEX_Over_UART.h:60
Definition: Protocol_Base.h:57
Communication protocol CANopen over CAN class.
Definition: Protocol_CANopen_Slave_Over_CAN.h:60
Communication protocol IP over ETHERNET class.
Definition: Protocol_IP_Over_ETHERNET.h:61
Communication protocol MODBUS RTU over UART class.
Definition: Protocol_MODBUS_Over_UART.h:82
Dummy communication protocol over UART class implementation.
Definition: Protocol_PLUG_Over_UART.h:54
STM32F429 RTC class.
Definition: RTC_STM32F429.h:71
NAND memory hardware driver.
Definition: S25FL512.h:62
On chip SPI4 bus master unit class.
Definition: SPI4_P017_39_KG3_CB.h:53
On chip SPI5 bus master unit class.
Definition: SPI5_P017_39_KG3_CB.h:53
SPI master base class.
Definition: SPI_Master_Base.h:58
STM32F429 stack class.
Definition: STACK_STM32F429.h:63
STM32F429 interval timer class.
Definition: SYSTICK_STM32F429.h:55
Signal recorder class.
Definition: Signal_Recorder.h:135
System timer class.
Definition: TIMER2_STM32F429.h:55
Target P017_39_KG3_CB class.
Definition: P017_39_KG3_CB.h:61
STM32F429 on-chip UART1 hardware abstraction layer class for P017_39_KG3_CB.
Definition: UART1_P017_39_KG3_CB.h:97
STM32F429 on-chip UART6 hardware abstraction layer class for P017_39_KG3_CB.
Definition: UART6_P017_39_KG3_CB.h:95
STM32F429 on-chip UART7 hardware abstraction layer class for P017_39_KG3_CB.
Definition: UART7_P017_39_KG3_CB.h:95
STM32F429 on-chip WDT module class.
Definition: WDT_STM32F429.h:70