11 #if __ARMCC_VERSION >= 6000000
12 __asm(
".global __use_no_semihosting");
13 #elif __ARMCC_VERSION >= 5000000
14 #pragma import(__use_no_semihosting)
16 #error Unsupported compiler
113 #define SPI2_MODULE_INSTALLED (true)
132 #ifndef ADC_MODULE_INSTALLED
139 #error "ERROR: Undefined compilation switch: ADC_MODULE_INSTALLED"
153 #ifndef DAC_MODULE_INSTALLED
160 #error "ERROR: Undefined compilation switch: DAC_MODULE_INSTALLED"
174 #ifndef DIO_MODULE_INSTALLED
181 #error "ERROR: Undefined compilation switch: DIO_MODULE_INSTALLED"
195 #ifndef FPGA_MODULE_INSTALLED
202 #error "ERROR: Undefined compilation switch: FPGA_MODULE_INSTALLED"
217 #if ( FPGA_MODULE_INSTALLED == (true) )
224 #define FPGA_BASE ((U32)0x60000000)
232 #define FPGA_ADDRESS_SLOT_SIZE (0x40)
235 #define FPGA_BACKPLANE_SLOT_AREA_OFFSET (U32)0x00001000
238 #define FPGA_INTERNAL_SLOT_AREA_OFFSET (U32)0x00000000
242 #define FPGA_BACKPLANE_SLOT_1 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 0 * FPGA_ADDRESS_SLOT_SIZE ) )
243 #define FPGA_BACKPLANE_SLOT_2 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 1 * FPGA_ADDRESS_SLOT_SIZE ) )
244 #define FPGA_BACKPLANE_SLOT_3 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 2 * FPGA_ADDRESS_SLOT_SIZE ) )
245 #define FPGA_BACKPLANE_SLOT_4 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 3 * FPGA_ADDRESS_SLOT_SIZE ) )
246 #define FPGA_BACKPLANE_SLOT_5 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 4 * FPGA_ADDRESS_SLOT_SIZE ) )
247 #define FPGA_BACKPLANE_SLOT_6 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 5 * FPGA_ADDRESS_SLOT_SIZE ) )
248 #define FPGA_BACKPLANE_SLOT_7 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 6 * FPGA_ADDRESS_SLOT_SIZE ) )
249 #define FPGA_BACKPLANE_SLOT_8 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 7 * FPGA_ADDRESS_SLOT_SIZE ) )
250 #define FPGA_BACKPLANE_SLOT_9 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 8 * FPGA_ADDRESS_SLOT_SIZE ) )
251 #define FPGA_BACKPLANE_SLOT_10 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 9 * FPGA_ADDRESS_SLOT_SIZE ) )
252 #define FPGA_BACKPLANE_SLOT_11 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 10 * FPGA_ADDRESS_SLOT_SIZE ) )
253 #define FPGA_BACKPLANE_SLOT_12 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 11 * FPGA_ADDRESS_SLOT_SIZE ) )
254 #define FPGA_BACKPLANE_SLOT_13 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 12 * FPGA_ADDRESS_SLOT_SIZE ) )
255 #define FPGA_BACKPLANE_SLOT_14 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 13 * FPGA_ADDRESS_SLOT_SIZE ) )
256 #define FPGA_BACKPLANE_SLOT_15 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 14 * FPGA_ADDRESS_SLOT_SIZE ) )
257 #define FPGA_BACKPLANE_SLOT_16 ( FPGA_BASE + FPGA_BACKPLANE_SLOT_AREA_OFFSET + ( 15 * FPGA_ADDRESS_SLOT_SIZE ) )
259 #define FPGA_INTERNAL_SLOT_1 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 0 * FPGA_ADDRESS_SLOT_SIZE ) )
260 #define FPGA_INTERNAL_SLOT_2 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 1 * FPGA_ADDRESS_SLOT_SIZE ) )
261 #define FPGA_INTERNAL_SLOT_3 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 2 * FPGA_ADDRESS_SLOT_SIZE ) )
262 #define FPGA_INTERNAL_SLOT_4 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 3 * FPGA_ADDRESS_SLOT_SIZE ) )
263 #define FPGA_INTERNAL_SLOT_5 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 4 * FPGA_ADDRESS_SLOT_SIZE ) )
264 #define FPGA_INTERNAL_SLOT_6 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 5 * FPGA_ADDRESS_SLOT_SIZE ) )
265 #define FPGA_INTERNAL_SLOT_7 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 6 * FPGA_ADDRESS_SLOT_SIZE ) )
266 #define FPGA_INTERNAL_SLOT_8 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 7 * FPGA_ADDRESS_SLOT_SIZE ) )
267 #define FPGA_INTERNAL_SLOT_9 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 8 * FPGA_ADDRESS_SLOT_SIZE ) )
268 #define FPGA_INTERNAL_SLOT_10 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 9 * FPGA_ADDRESS_SLOT_SIZE ) )
269 #define FPGA_INTERNAL_SLOT_11 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 10 * FPGA_ADDRESS_SLOT_SIZE ) )
270 #define FPGA_INTERNAL_SLOT_12 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 11 * FPGA_ADDRESS_SLOT_SIZE ) )
271 #define FPGA_INTERNAL_SLOT_13 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 12 * FPGA_ADDRESS_SLOT_SIZE ) )
272 #define FPGA_INTERNAL_SLOT_14 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 13 * FPGA_ADDRESS_SLOT_SIZE ) )
273 #define FPGA_INTERNAL_SLOT_15 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 14 * FPGA_ADDRESS_SLOT_SIZE ) )
274 #define FPGA_INTERNAL_SLOT_16 ( FPGA_BASE + FPGA_INTERNAL_SLOT_AREA_OFFSET + ( 15 * FPGA_ADDRESS_SLOT_SIZE ) )
284 #ifndef COM0_MODULE_INSTALLED
291 #error "ERROR: Undefined compilation switch: COM0_MODULE_INSTALLED"
301 extern TCOM0 object_System_COM0;
303 #if ( COM0_MODULE_INSTALLED == (true) )
319 #ifndef COM1_COMMUNICATION_MODE
326 #error "ERROR: Undefined compilation switch: COM1_COMMUNICATION_MODE"
338 extern "C" VOID System_UART1_Interrupt_Handler();
340 #if ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_NONE )
351 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX )
362 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_V2 )
373 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_MASTER )
384 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_RTU )
395 #elif ( COM1_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_ASCII )
405 #error "ERROR: MODBUS ASCII communication mode not implemented for COM1."
414 #error "ERROR: Undefined or unknown communication mode for COM1."
424 #ifndef COM2_COMMUNICATION_MODE
431 #error "ERROR: Undefined compilation switch: COM2_COMMUNICATION_MODE"
443 extern "C" VOID System_UART6_Interrupt_Handler();
445 #if ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_NONE )
454 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX )
463 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_V2 )
472 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX_MASTER )
481 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_RTU )
490 #elif ( COM2_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_ASCII )
500 #error "ERROR: MODBUS ASCII communication mode not implemented for COM2."
509 #error "ERROR: Undefined or unknown communication mode for COM2."
519 #ifndef COM3_COMMUNICATION_MODE
526 #error "ERROR: Undefined compilation switch: COM3_COMMUNICATION_MODE"
536 #if ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_NONE )
545 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_ANVILEX )
555 #error "ERROR: ANVILEX communication mode not supported on COM3."
557 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_RTU )
567 #error "ERROR: MODBUS RTU communication mode not supported on COM3."
569 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_MODBUS_ASCII )
579 #error "ERROR: MODBUS ASCII communication mode not supported on COM3."
581 #elif ( COM3_COMMUNICATION_MODE == USART_COMMUNICATION_MODE_SIMCOM )
591 #error "ERROR: SIMCOM communication mode not supported on COM3."
600 #error "ERROR: Undefined or unknown communication mode for COM3."
610 #ifndef ETHERNET_MODULE_INSTALLED
617 #error "ERROR: Undefined compilation switch: ETHERNET_MODULE_INSTALLED"
629 extern "C" VOID System_ETH_Interrupt_Handler();
631 #if ( ETHERNET_MODULE_INSTALLED == true )
645 #error "ERROR: Undefined or unknown communication mode for ETHERNET."
655 #ifndef CAN1_MODULE_INSTALLED
662 #error "ERROR: Undefined compilation switch: CAN1_MODULE_INSTALLED"
675 extern "C" VOID System_CAN1_RX0_Interrupt_Handler();
676 extern "C" VOID System_CAN1_RX1_Interrupt_Handler();
677 extern "C" VOID System_CAN1_TX_Interrupt_Handler();
678 extern "C" VOID System_CAN1_SCE_Interrupt_Handler();
679 extern "C" VOID System_CAN2_RX0_Interrupt_Handler();
680 extern "C" VOID System_CAN2_RX1_Interrupt_Handler();
681 extern "C" VOID System_CAN2_TX_Interrupt_Handler();
682 extern "C" VOID System_CAN2_SCE_Interrupt_Handler();
684 #if ( CAN1_MODULE_INSTALLED == (true) )
701 #error "ERROR: Undefined or unknown communication mode for CAN1."
711 #ifndef ADDISIONAL_MODULE_COMMUNICATION
718 #error "ERROR: Undefined compilation switch: ADDISIONAL_MODULE_COMMUNICATION"
727 #if ( ADDISIONAL_MODULE_COMMUNICATION == PB_DPV_1 )
758 #error "ERROR: Undefined or unknown communication mode for ANYBUS."
783 #ifndef COMMAND_MANAGER_MODULE_INSTALLED
790 #error "ERROR: Undefined compilation switch: COMMAND_MANAGER_MODULE_INSTALLED"
799 #if ( COMMAND_MANAGER_MODULE_INSTALLED == (true) )
818 #ifndef EVENT_MANAGER_MODULE_INSTALLED
825 #error "ERROR: Undefined compilation switch: EVENT_MANAGER_MODULE_INSTALLED"
834 #if ( EVENT_MANAGER_MODULE_INSTALLED == (true) )
842 #define EVENT_DATABASE_STORAGE_INSTALLED (true)
846 extern TS25FL512 *object_Event_Database_Storage;
861 #ifndef SCOPE_MODULE_INSTALLED
868 #error "ERROR: Undefined compilation switch: SCOPE_MODULE_INSTALLED"
877 #if ( SCOPE_MODULE_INSTALLED == (true) )
ANYBUS module base class header file.
ANYBUS Profibus module driver class header file.
Control board P015.09 CB STM32F429 on-chip CAN1 hardware driver header file.
STM32F429 CPU class header file.
ConOpSys command manager class header file.
void VOID
Datatypesess datatype definition.
Definition: Defines.h:105
Control board P015.09 CB STM32F429 on-chip ETHERNET hardware driver header file.
Event manager class header file.
NVRAM chip FM25V02 hardware driver class header file.
Control board P015.09 CB FPGA hardware driver header file.
Function block manager class header file.
STM32F429 heap class header file.
Control board P015.09 CB on-board system LED hardware driver header file.
STM32F429 on-chip NVIC module class header file.
VOID FPGA_Interrupt_Handler()
Definition: P013_35_V1_3_CPU.cpp:117
Control board P015.09 V1.0 hardware driver header file.
ConOpSys parameter database manager class header file.
Communication protocol ANVILEX master over UART class header file.
Communication protocol ANVILEX over UART class header file.
Communication protocol ANVILEX over UART class header file.
Communication protocol CANopen over CAN class header file.
Communication protocol IP over Ethernet class header file.
Communication protocol MODBUS RTU over UART class header file.
Dummy communication protocol over UART class header file.
STM32F429 on-chip RTC module class header file.
SPI NAND FLASH memory chip S25FL512 hardware driver class header file.
Control board P015.09 CB STM32F429 on-chip SPI2 hardware driver header file.
Control board P015.09 CB STM32F429 on-chip SPI1 hardware driver header file.
Control board P015.09 CB STM32F429 on-chip SPI5 hardware driver header file.
STM32F429 stack class header file.
STM32F429 on-chip SYSTICK timer module class header file.
Signal recorder class header file.
Virtual communication link COM0 class header file.
TABCC_DPV1 object_ABCC
ABCC global object instance.
Definition: System_Resource.cpp:1452
TProtocol_PLUG_Over_UART object_Protocol_Over_COM0
Definition: System_Resource.cpp:1177
TProtocol_CANopen_Slave_Over_CAN object_Protocol_Over_CAN
CANopen slave protocol over CAN global object instance.
Definition: System_Resource.cpp:1438
TCommand_Manager object_Command_Manager
Command manager global object instance.
Definition: System_Resource.cpp:1464
TProtocol_IP_Over_ETHERNET object_Protocol_Over_ETHERNET
IP protocol over ETHERNET global object instance.
Definition: System_Resource.cpp:1427
STM32F429 on-chip TIMER2 module class header file.
Control board P015.09 CB STM32F429 on-chip UART1 hardware driver header file.
Control board P015.09 CB STM32F429 on-chip UART6 hardware driver header file.
STM32F429 on-chip WTD module class header file.
Definition: ABCC_DPV1.h:111
STM32F429 on-chip CAN1 hardware abstraction layer class for P015.09 CB board.
Definition: CAN1_P015_09_CB.h:58
Virtual communication link COM0 class.
Definition: System_COM0.h:91
STM32F429 CPU hardware class.
Definition: CPU_STM32F429.h:69
ConOpSys terminal command manager class.
Definition: Command_Manager.h:86
STM32F429 on-chip Ethernet hardware abstraction layer class for P015_09_CB.
Definition: ETHERNET_P015_09_CB.h:98
Event manager class.
Definition: Event_Manager.h:70
FPGA hardware dependent driver class for P015_09_CB.
Definition: FPGA_P015_09_CB.h:78
STM32F429 heap class.
Definition: HEAP_STM32F429.h:63
P015.09 control board system LED class.
Definition: LED_P015_09_CB.h:58
Communication protocol ANVILEX master over UART class.
Definition: Protocol_ANVILEX_Master_Over_UART.h:62
Communication protocol ANVILEX over UART class.
Definition: Protocol_ANVILEX_Over_UART_V2.h:62
Communication protocol ANVILEX over UART class.
Definition: Protocol_ANVILEX_Over_UART.h:60
Definition: Protocol_Base.h:57
Communication protocol CANopen over CAN class.
Definition: Protocol_CANopen_Slave_Over_CAN.h:60
Communication protocol IP over ETHERNET class.
Definition: Protocol_IP_Over_ETHERNET.h:61
Communication protocol MODBUS RTU over UART class.
Definition: Protocol_MODBUS_Over_UART.h:82
Dummy communication protocol over UART class implementation.
Definition: Protocol_PLUG_Over_UART.h:54
STM32F429 RTC class.
Definition: RTC_STM32F429.h:71
NAND memory hardware driver.
Definition: S25FL512.h:62
On chip SPI4 bus master unit class.
Definition: SPI4_P015_09_CB.h:56
On chip SPI5 bus master unit class.
Definition: SPI5_P015_09_CB.h:56
SPI master base class.
Definition: SPI_Master_Base.h:58
STM32F429 stack class.
Definition: STACK_STM32F429.h:63
STM32F429 interval timer class.
Definition: SYSTICK_STM32F429.h:55
Signal recorder class.
Definition: Signal_Recorder.h:135
System timer class.
Definition: TIMER2_STM32F429.h:55
Target P017_39_KG3_CB_DEBUG class.
Definition: P015_09_V1_0.h:64
STM32F429 on-chip UART1 hardware abstraction layer class for P015_09_CB.
Definition: UART1_P015_09_CB.h:100
STM32F429 on-chip UART6 hardware abstraction layer class for P015_09_CB.
Definition: UART6_P015_09_CB.h:98
STM32F429 on-chip WDT module class.
Definition: WDT_STM32F429.h:70