Macros | |
| #define | ETH_DMATXDESC_OWN 0x80000000U |
| Bit definition of TDES0 register: DMA Tx descriptor status register. More... | |
| #define | ETH_DMATXDESC_IC 0x40000000U |
| #define | ETH_DMATXDESC_LS 0x20000000U |
| #define | ETH_DMATXDESC_FS 0x10000000U |
| #define | ETH_DMATXDESC_DC 0x08000000U |
| #define | ETH_DMATXDESC_DP 0x04000000U |
| #define | ETH_DMATXDESC_TTSE 0x02000000U |
| #define | ETH_DMATXDESC_CIC 0x00C00000U |
| #define | ETH_DMATXDESC_CIC_BYPASS 0x00000000U |
| #define | ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U |
| #define | ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U |
| #define | ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U |
| #define | ETH_DMATXDESC_TER 0x00200000U |
| #define | ETH_DMATXDESC_TCH 0x00100000U |
| #define | ETH_DMATXDESC_TTSS 0x00020000U |
| #define | ETH_DMATXDESC_IHE 0x00010000U |
| #define | ETH_DMATXDESC_ES 0x00008000U |
| #define | ETH_DMATXDESC_JT 0x00004000U |
| #define | ETH_DMATXDESC_FF 0x00002000U |
| #define | ETH_DMATXDESC_PCE 0x00001000U |
| #define | ETH_DMATXDESC_LCA 0x00000800U |
| #define | ETH_DMATXDESC_NC 0x00000400U |
| #define | ETH_DMATXDESC_LCO 0x00000200U |
| #define | ETH_DMATXDESC_EC 0x00000100U |
| #define | ETH_DMATXDESC_VF 0x00000080U |
| #define | ETH_DMATXDESC_CC 0x00000078U |
| #define | ETH_DMATXDESC_ED 0x00000004U |
| #define | ETH_DMATXDESC_UF 0x00000002U |
| #define | ETH_DMATXDESC_DB 0x00000001U |
| #define | ETH_DMATXDESC_TBS2 0x1FFF0000U |
| Bit definition of TDES1 register. More... | |
| #define | ETH_DMATXDESC_TBS1 0x00001FFFU |
| #define | ETH_DMATXDESC_B1AP 0xFFFFFFFFU |
| Bit definition of TDES2 register. More... | |
| #define | ETH_DMATXDESC_B2AP 0xFFFFFFFFU |
| Bit definition of TDES3 register. More... | |
| #define | ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ |
| #define | ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ |
Detailed Description
Macro Definition Documentation
◆ ETH_DMAPTPTXDESC_TTSH
| #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ |
◆ ETH_DMAPTPTXDESC_TTSL
| #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ |
◆ ETH_DMATXDESC_B1AP
| #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU |
Bit definition of TDES2 register.
Buffer1 Address Pointer
◆ ETH_DMATXDESC_B2AP
| #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU |
Bit definition of TDES3 register.
Buffer2 Address Pointer
◆ ETH_DMATXDESC_CC
| #define ETH_DMATXDESC_CC 0x00000078U |
Collision Count
◆ ETH_DMATXDESC_CIC
| #define ETH_DMATXDESC_CIC 0x00C00000U |
Checksum Insertion Control: 4 cases
◆ ETH_DMATXDESC_CIC_BYPASS
| #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U |
Do Nothing: Checksum Engine is bypassed
◆ ETH_DMATXDESC_CIC_IPV4HEADER
| #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U |
IPV4 header Checksum Insertion
◆ ETH_DMATXDESC_CIC_TCPUDPICMP_FULL
| #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U |
TCP/UDP/ICMP Checksum Insertion fully calculated
◆ ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT
| #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U |
TCP/UDP/ICMP Checksum Insertion calculated over segment only
◆ ETH_DMATXDESC_DB
| #define ETH_DMATXDESC_DB 0x00000001U |
Deferred Bit
◆ ETH_DMATXDESC_DC
| #define ETH_DMATXDESC_DC 0x08000000U |
Disable CRC
◆ ETH_DMATXDESC_DP
| #define ETH_DMATXDESC_DP 0x04000000U |
Disable Padding
◆ ETH_DMATXDESC_EC
| #define ETH_DMATXDESC_EC 0x00000100U |
Excessive Collision: transmission aborted after 16 collisions
◆ ETH_DMATXDESC_ED
| #define ETH_DMATXDESC_ED 0x00000004U |
Excessive Deferral
◆ ETH_DMATXDESC_ES
| #define ETH_DMATXDESC_ES 0x00008000U |
Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
◆ ETH_DMATXDESC_FF
| #define ETH_DMATXDESC_FF 0x00002000U |
Frame Flushed: DMA/MTL flushed the frame due to SW flush
◆ ETH_DMATXDESC_FS
| #define ETH_DMATXDESC_FS 0x10000000U |
First Segment
◆ ETH_DMATXDESC_IC
| #define ETH_DMATXDESC_IC 0x40000000U |
Interrupt on Completion
◆ ETH_DMATXDESC_IHE
| #define ETH_DMATXDESC_IHE 0x00010000U |
IP Header Error
◆ ETH_DMATXDESC_JT
| #define ETH_DMATXDESC_JT 0x00004000U |
Jabber Timeout
◆ ETH_DMATXDESC_LCA
| #define ETH_DMATXDESC_LCA 0x00000800U |
Loss of Carrier: carrier lost during transmission
◆ ETH_DMATXDESC_LCO
| #define ETH_DMATXDESC_LCO 0x00000200U |
Late Collision: transmission aborted due to collision
◆ ETH_DMATXDESC_LS
| #define ETH_DMATXDESC_LS 0x20000000U |
Last Segment
◆ ETH_DMATXDESC_NC
| #define ETH_DMATXDESC_NC 0x00000400U |
No Carrier: no carrier signal from the transceiver
◆ ETH_DMATXDESC_OWN
| #define ETH_DMATXDESC_OWN 0x80000000U |
Bit definition of TDES0 register: DMA Tx descriptor status register.
OWN bit: descriptor is owned by DMA engine
◆ ETH_DMATXDESC_PCE
| #define ETH_DMATXDESC_PCE 0x00001000U |
Payload Checksum Error
◆ ETH_DMATXDESC_TBS1
| #define ETH_DMATXDESC_TBS1 0x00001FFFU |
Transmit Buffer1 Size
◆ ETH_DMATXDESC_TBS2
| #define ETH_DMATXDESC_TBS2 0x1FFF0000U |
Bit definition of TDES1 register.
Transmit Buffer2 Size
◆ ETH_DMATXDESC_TCH
| #define ETH_DMATXDESC_TCH 0x00100000U |
Second Address Chained
◆ ETH_DMATXDESC_TER
| #define ETH_DMATXDESC_TER 0x00200000U |
Transmit End of Ring
◆ ETH_DMATXDESC_TTSE
| #define ETH_DMATXDESC_TTSE 0x02000000U |
Transmit Time Stamp Enable
◆ ETH_DMATXDESC_TTSS
| #define ETH_DMATXDESC_TTSS 0x00020000U |
Tx Time Stamp Status
◆ ETH_DMATXDESC_UF
| #define ETH_DMATXDESC_UF 0x00000002U |
Underflow Error: late data arrival from the memory
◆ ETH_DMATXDESC_VF
| #define ETH_DMATXDESC_VF 0x00000080U |
VLAN Frame
