Collaboration diagram for ETH DMA RX Descriptor:
Macros | |
| #define | ETH_DMARXDESC_OWN 0x80000000U |
| Bit definition of RDES0 register: DMA Rx descriptor status register. More... | |
| #define | ETH_DMARXDESC_AFM 0x40000000U |
| #define | ETH_DMARXDESC_FL 0x3FFF0000U |
| #define | ETH_DMARXDESC_ES 0x00008000U |
| #define | ETH_DMARXDESC_DE 0x00004000U |
| #define | ETH_DMARXDESC_SAF 0x00002000U |
| #define | ETH_DMARXDESC_LE 0x00001000U |
| #define | ETH_DMARXDESC_OE 0x00000800U |
| #define | ETH_DMARXDESC_VLAN 0x00000400U |
| #define | ETH_DMARXDESC_FS 0x00000200U |
| #define | ETH_DMARXDESC_LS 0x00000100U |
| #define | ETH_DMARXDESC_IPV4HCE 0x00000080U |
| #define | ETH_DMARXDESC_LC 0x00000040U |
| #define | ETH_DMARXDESC_FT 0x00000020U |
| #define | ETH_DMARXDESC_RWT 0x00000010U |
| #define | ETH_DMARXDESC_RE 0x00000008U |
| #define | ETH_DMARXDESC_DBE 0x00000004U |
| #define | ETH_DMARXDESC_CE 0x00000002U |
| #define | ETH_DMARXDESC_MAMPCE 0x00000001U |
| #define | ETH_DMARXDESC_DIC 0x80000000U |
| Bit definition of RDES1 register. More... | |
| #define | ETH_DMARXDESC_RBS2 0x1FFF0000U |
| #define | ETH_DMARXDESC_RER 0x00008000U |
| #define | ETH_DMARXDESC_RCH 0x00004000U |
| #define | ETH_DMARXDESC_RBS1 0x00001FFFU |
| #define | ETH_DMARXDESC_B1AP 0xFFFFFFFFU |
| Bit definition of RDES2 register. More... | |
| #define | ETH_DMARXDESC_B2AP 0xFFFFFFFFU |
| Bit definition of RDES3 register. More... | |
| #define | ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ |
| #define | ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ |
| #define | ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ |
| #define | ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ |
| #define | ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ |
| #define | ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ |
| #define | ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ |
| #define | ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ |
| #define | ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ |
| #define | ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ |
| #define | ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ |
| #define | ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ |
| #define | ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ |
| #define | ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ |
| #define | ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ |
Detailed Description
Macro Definition Documentation
◆ ETH_DMAPTPRXDESC_IPCB
| #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ |
◆ ETH_DMAPTPRXDESC_IPHE
| #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ |
◆ ETH_DMAPTPRXDESC_IPPE
| #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ |
◆ ETH_DMAPTPRXDESC_IPPT
| #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ |
◆ ETH_DMAPTPRXDESC_IPPT_ICMP
| #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ |
◆ ETH_DMAPTPRXDESC_IPPT_TCP
| #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ |
◆ ETH_DMAPTPRXDESC_IPPT_UDP
| #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ |
◆ ETH_DMAPTPRXDESC_IPV4PR
| #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ |
◆ ETH_DMAPTPRXDESC_IPV6PR
| #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ |
◆ ETH_DMAPTPRXDESC_PTPFT
| #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ |
◆ ETH_DMAPTPRXDESC_PTPMT
| #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ |
◆ ETH_DMAPTPRXDESC_PTPMT_DELAYREQ
| #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ |
◆ ETH_DMAPTPRXDESC_PTPMT_DELAYRESP
| #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ |
◆ ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP
| #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ |
◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE
| #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ |
◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG
| #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ |
◆ ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL
| #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ |
◆ ETH_DMAPTPRXDESC_PTPMT_SYNC
| #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ |
◆ ETH_DMAPTPRXDESC_PTPV
| #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ |
◆ ETH_DMAPTPRXDESC_RTSH
| #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ |
◆ ETH_DMAPTPRXDESC_RTSL
| #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ |
◆ ETH_DMARXDESC_AFM
| #define ETH_DMARXDESC_AFM 0x40000000U |
DA Filter Fail for the rx frame
◆ ETH_DMARXDESC_B1AP
| #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU |
Bit definition of RDES2 register.
Buffer1 Address Pointer
◆ ETH_DMARXDESC_B2AP
| #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU |
Bit definition of RDES3 register.
Buffer2 Address Pointer
◆ ETH_DMARXDESC_CE
| #define ETH_DMARXDESC_CE 0x00000002U |
CRC error
◆ ETH_DMARXDESC_DBE
| #define ETH_DMARXDESC_DBE 0x00000004U |
Dribble bit error: frame contains non int multiple of 8 bits
◆ ETH_DMARXDESC_DE
| #define ETH_DMARXDESC_DE 0x00004000U |
Descriptor error: no more descriptors for receive frame
◆ ETH_DMARXDESC_DIC
| #define ETH_DMARXDESC_DIC 0x80000000U |
Bit definition of RDES1 register.
Disable Interrupt on Completion
◆ ETH_DMARXDESC_ES
| #define ETH_DMARXDESC_ES 0x00008000U |
Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
◆ ETH_DMARXDESC_FL
| #define ETH_DMARXDESC_FL 0x3FFF0000U |
Receive descriptor frame length
◆ ETH_DMARXDESC_FS
| #define ETH_DMARXDESC_FS 0x00000200U |
First descriptor of the frame
◆ ETH_DMARXDESC_FT
| #define ETH_DMARXDESC_FT 0x00000020U |
Frame type - Ethernet, otherwise 802.3
◆ ETH_DMARXDESC_IPV4HCE
| #define ETH_DMARXDESC_IPV4HCE 0x00000080U |
IPC Checksum Error: Rx Ipv4 header checksum error
◆ ETH_DMARXDESC_LC
| #define ETH_DMARXDESC_LC 0x00000040U |
Late collision occurred during reception
◆ ETH_DMARXDESC_LE
| #define ETH_DMARXDESC_LE 0x00001000U |
Frame size not matching with length field
◆ ETH_DMARXDESC_LS
| #define ETH_DMARXDESC_LS 0x00000100U |
Last descriptor of the frame
◆ ETH_DMARXDESC_MAMPCE
| #define ETH_DMARXDESC_MAMPCE 0x00000001U |
Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
◆ ETH_DMARXDESC_OE
| #define ETH_DMARXDESC_OE 0x00000800U |
Overflow Error: Frame was damaged due to buffer overflow
◆ ETH_DMARXDESC_OWN
| #define ETH_DMARXDESC_OWN 0x80000000U |
Bit definition of RDES0 register: DMA Rx descriptor status register.
OWN bit: descriptor is owned by DMA engine
◆ ETH_DMARXDESC_RBS1
| #define ETH_DMARXDESC_RBS1 0x00001FFFU |
Receive Buffer1 Size
◆ ETH_DMARXDESC_RBS2
| #define ETH_DMARXDESC_RBS2 0x1FFF0000U |
Receive Buffer2 Size
◆ ETH_DMARXDESC_RCH
| #define ETH_DMARXDESC_RCH 0x00004000U |
Second Address Chained
◆ ETH_DMARXDESC_RE
| #define ETH_DMARXDESC_RE 0x00000008U |
Receive error: error reported by MII interface
◆ ETH_DMARXDESC_RER
| #define ETH_DMARXDESC_RER 0x00008000U |
Receive End of Ring
◆ ETH_DMARXDESC_RWT
| #define ETH_DMARXDESC_RWT 0x00000010U |
Receive Watchdog Timeout: watchdog timer expired during reception
◆ ETH_DMARXDESC_SAF
| #define ETH_DMARXDESC_SAF 0x00002000U |
SA Filter Fail for the received frame
◆ ETH_DMARXDESC_VLAN
| #define ETH_DMARXDESC_VLAN 0x00000400U |
VLAN Tag: received frame is a VLAN frame
