Target_P017_11_V1.h

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//------------------------------------------------------------------------------
//! @file       Target_P017_11_V1.h
//! @brief      Target board P017.11 V1 hardware driver header file.
//! @attention  No special attention requered.
//! @copyright  (C) 2015-2020 ANVILEX LLC
//!             $HeadURL: https://192.168.3.4:8443/svn/P004_07/ConOpSys/Hardware/P017_11_V1/Target_P017_11_V1.h $
//!             $Revision: 2280 $
//!             $Date: 2020-12-12 16:29:27 +0500 (Sa, 12 Dez 2020) $
//!             $Author: minch $
//------------------------------------------------------------------------------
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
//    this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of ANVILEX nor the names of its contributors may be
//    used to endorse or promote products derived from this software without
//    specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Protecting header files from mutual, recursive inclusion.
//------------------------------------------------------------------------------
 
#pragma once
 
//------------------------------------------------------------------------------
// Include system headers
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include project headers
//------------------------------------------------------------------------------
 
#include "Target_Base.h"
 
//------------------------------------------------------------------------------
// FPGA base address
//------------------------------------------------------------------------------
  
#define FPGA_BASE (0x60000000)
//#define FPGA_SIZE (0x00010000)
 
//------------------------------------------------------------------------------
// Slot base address definitions
//------------------------------------------------------------------------------
  
#define FPGA_MODULE_EXTERNAL_SLOT_1_BASE_ADDRESS          (FPGA_BASE+(0x00000020))
#define FPGA_MODULE_EXTERNAL_SLOT_2_BASE_ADDRESS          (FPGA_BASE+(0x00000040))
#define FPGA_MODULE_EXTERNAL_SLOT_3_BASE_ADDRESS          (FPGA_BASE+(0x00000060))
#define FPGA_MODULE_EXTERNAL_SLOT_4_BASE_ADDRESS          (FPGA_BASE+(0x00000080))
#define FPGA_MODULE_EXTERNAL_SLOT_6_BASE_ADDRESS          (FPGA_BASE+(0x000000A0))
#define FPGA_MODULE_EXTERNAL_SLOT_11_BASE_ADDRESS         (FPGA_BASE+(0x000000C0))
#define FPGA_MODULE_EXTERNAL_SLOT_12_BASE_ADDRESS         (FPGA_BASE+(0x000000E0))
#define FPGA_MODULE_EXTERNAL_SLOT_13_BASE_ADDRESS         (FPGA_BASE+(0x00000100))
#define FPGA_MODULE_EXTERNAL_SLOT_14_BASE_ADDRESS         (FPGA_BASE+(0x00000120))
#define FPGA_MODULE_EXTERNAL_SLOT_16_BASE_ADDRESS         (FPGA_BASE+(0x00000140))
#define FPGA_MODULE_EXTERNAL_SLOT_17_BASE_ADDRESS         (FPGA_BASE+(0x00000160))
 
#define FPGA_MODULE_INTERNAL_SLOT_1_BASE_ADDRESS          (FPGA_BASE+(0x00000180))
#define FPGA_MODULE_INTERNAL_SLOT_2_BASE_ADDRESS          (FPGA_BASE+(0x000001A0))
 
//------------------------------------------------------------------------------
// 
//------------------------------------------------------------------------------
 
class TTarget_P017_11_V1 : public TTarget_Base
{
 
  //----------------------------------------------------------------------------
  // Public methods, variables and definitions
  //----------------------------------------------------------------------------
 
  public:
 
    // Initialization and finalization methods
    VOID Init(); //!< Initialisation method
    VOID Done(); //!< Finalisation method
 
    // Core clock 
    VOID System_Core_Clock_Update();
    U32 Get_SYSCLK_Frequency();
    U32 Get_HCLK_Frequency();
    U32 Get_PCLK1_Frequency();
    U32 Get_PCLK2_Frequency();
    U32 Get_TCLK1_Frequency();
    U32 Get_TCLK2_Frequency();
    U32 Get_IWDG_Frequency();
 
    virtual BOOL FPGA_Configure();
 
  virtual U32 Get_CPU_Reset_Source();
  virtual TTarget_Base::TReset_Source Get_Reset_Source();
  virtual U32 Get_CPU_Device_ID();
  virtual U32 Get_CPU_Revision();
  virtual U32 Get_CPU_Unique_Device_ID( U32 u32_Index );
  virtual U32 Get_CPU_Flash_Size();
  virtual U32 Get_CPU_RAM_Size();
 
  virtual U32 Get_CPU_Stack_Base();
  virtual U32 Get_CPU_Stack_Size();
 
  virtual U32 Get_CPU_Heap_Base();
  virtual U32 Get_CPU_Heap_Size();
 
    // Interrupt management methods
    virtual VOID FPGA_Interrupt_Enable( U32 u32_TickPriority ); //!< Enable interrupt method
    virtual VOID FPGA_Interrupt_Disable(); //!< Disable interrupt method
    
    // Register generic access methods
    virtual VOID FPGA_Write_U16( U16 u16_Address, U16 u16_Value ); //!< Write 16 bit data into FPGA register
    virtual VOID FPGA_Read_U16( U16 u16_Address, U16 *u16_Value ); //!< Read 16 bit data from FPGA register
 
  //----------------------------------------------------------------------------
  // Protected methods, variables and definitions
  //----------------------------------------------------------------------------
 
  protected:
 
  //----------------------------------------------------------------------------
  // Private methods, variables and definitions
  //----------------------------------------------------------------------------
  
  private:
 
    // System Clock Frequency (Core Clock)
    U32 u32_SYSCLK;
    U32 u32_HCLK;
    U32 u32_PCLK1;
    U32 u32_PCLK2;
    U32 u32_TCLK1;
    U32 u32_TCLK2;
    U32 u32_IWDG;
  
    // Error flag
    U32 u32_Error_Flag;
 
};
 
//------------------------------------------------------------------------------
// Export external references
//------------------------------------------------------------------------------
 
extern "C" void System_Init( void );
 
extern "C" VOID FPGA_Interrupt_Handler();
 
//------------------------------------------------------------------------------
// End of file 
//------------------------------------------------------------------------------