ConOpSys V2970  P004.07
ANVILEX control operating system
PWM_2C3P2L.h
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1 //------------------------------------------------------------------------------
2 //! @file PWM_2C3P2L.h
3 //! @author ANVILEX GmbH
4 //! @version V1.0
5 //! @date 03.05.2016
6 //! @brief 3-phase 2-level pulse width modulator object header file.
7 //! @attention
8 //!
9 //! COPYRIGHT(C) 2015 ANVILEX GmbH
10 //!
11 //! Redistribution and use in source and binary forms, with or without
12 //! modification, are permitted provided that the following conditions are met:
13 //!
14 //! 1. Redistributions of source code must retain the above copyright notice,
15 //! this list of conditions and the following disclaimer.
16 //!
17 //! 2. Redistributions in binary form must reproduce the above copyright notice,
18 //! this list of conditions and the following disclaimer in the documentation
19 //! and/or other materials provided with the distribution.
20 //!
21 //! 3. Neither the name of ANVILEX nor the names of its contributors may be
22 //! used to endorse or promote products derived from this software without
23 //! specific prior written permission.
24 //!
25 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
29 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 //! POSSIBILITY OF SUCH DAMAGE.
36 //------------------------------------------------------------------------------
37 //
38 // TPWM_3P2L_T1
39 // TPWM_3P2L - used in DFIG project
40 //
41 //------------------------------------------------------------------------------
42 
43 //------------------------------------------------------------------------------
44 // Protecting header files from mutual, recursive inclusion.
45 //------------------------------------------------------------------------------
46 
47 #pragma once
48 
49 //------------------------------------------------------------------------------
50 // Include standard libraries header files
51 //------------------------------------------------------------------------------
52 
53 //------------------------------------------------------------------------------
54 // Include thrid party header files
55 //------------------------------------------------------------------------------
56 
57 //------------------------------------------------------------------------------
58 // Include ConOpSys header files
59 //------------------------------------------------------------------------------
60 
61 #include "Application_Resource_Configuration.h"
62 #include "Function_Block_Base.h"
63 
64 //------------------------------------------------------------------------------
65 // Include ConOpSys application header files
66 //------------------------------------------------------------------------------
67 
68 //------------------------------------------------------------------------------
69 // Check requered includes
70 //------------------------------------------------------------------------------
71 
72 //#ifndef __APPLICATION_RESOURCE_CONFIGURATION_H
73 //#error "System resourse configuration file not included."
74 //#endif
75 
76 //------------------------------------------------------------------------------
77 // Macros
78 //------------------------------------------------------------------------------
79 
80 //! @brief 3-phase 2-level pulse width modulator type 1 object class
82 {
83 
84  //----------------------------------------------------------------------------
85  // Public defines, methods and variables
86  //----------------------------------------------------------------------------
87 
88  public:
89 
90  // Register structure for generic access
91  typedef struct
92  {
93 
94  // Control and status registars
95  union
96  {
97  U16 u16_Control; //!< Offset 0x00, Twin PWM module control register
98  U16 u16_Status; //!< Offset 0x00, Twin PWM module status register
99  };
100 
101  // Configuration registers
102  union
103  {
104  U16 u16_Half_Periode; //!< Offset 0x01, Half PWM periode register
105  U16 u16_Status_Latch; //!< Offset 0x01, Status register latch
106  };
107  U16 u16_Dead_Time_Inverter_1; //!< Offset 0x02, Dead time register of the inverter 1
108  U16 u16_Dead_Time_Inverter_2; //!< Offset 0x03, Dead time register of the inverter 2
109 
110  // Inverter 1 PWM setpoint registers
111  I16 i16_Setpoint_Inverter_1_L1; //!< Offset 0x04, Set point of the inverter 1 leg 1
112  I16 i16_Setpoint_Inverter_1_L2; //!< Offset 0x05, Set point of the inverter 1 leg 2
113  I16 i16_Setpoint_Inverter_1_L3; //!< Offset 0x06, Set point of the inverter 1 leg 3
114  U16 u16_Reserve_7; //!< Offset 0x07, Not used
115 
116  // Inverter 2 PWM Setpoint registers
117  I16 i16_Setpoint_Inverter_2_L1; //!< Offset 0x08, Set point of the inverter 2 leg 1
118  I16 i16_Setpoint_Inverter_2_L2; //!< Offset 0x09, Set point of the inverter 2 leg 2
119  I16 i16_Setpoint_Inverter_2_L3; //!< Offset 0x0A, Set point of the inverter 2 leg 3
120  U16 u16_Reserve_B; //!< Offset 0x0B, Not used
121 
122  // Reserved registers
123  U16 u16_Reserve_C; //!< Offset 0x0C, Not used
124  U16 u16_Reserve_D; //!< Offset 0x0D, Not used
125  U16 u16_Reserve_E; //!< Offset 0x0E, Not used
126  U16 u16_Reserve_F; //!< Offset 0x0F, Not used
127 
129 
130  //--------------------------------------------------------------------------
131  // Public methods
132  //--------------------------------------------------------------------------
133 
134  TPWM_3P2L_T1(); //!< Constructor method
135 
136  //!-------------------------------------------------------------------------
137  //! @brief Class destructor method.
138  //! @note None
139  //! \par Override
140  //! Not allowed
141  //! @attention Don't call this method directly.
142  //--------------------------------------------------------------------------
143 
144  virtual ~TPWM_3P2L_T1();
145 
146  //!-------------------------------------------------------------------------
147  //! @brief 3-phase 3-level pulse width modulator memory mapping.
148  //! @note None
149  //! @param [in] struct_Registers_Base_Address Base address within FPGA address space
150  //! @return None
151  //! \par Override
152  //! Not allowed
153  //! @attention None
154  //--------------------------------------------------------------------------
155 
156  VOID Map( TPWM_3P2L_Registers *struct_Registers_Base_Address );
157 
158  //!-------------------------------------------------------------------------
159  //! @brief Function block initialisation method.
160  //! @note None
161  //! \par Override
162  //! Not allowed
163  //! @attention Don't call this method directly.
164  //--------------------------------------------------------------------------
165 
166  virtual VOID Init();
167 
168  //!-------------------------------------------------------------------------
169  //! @brief Function block execution method.
170  //! @note None
171  //! \par Override
172  //! Not allowed
173  //! @attention None
174  //--------------------------------------------------------------------------
175 
176  virtual VOID Execute();
177 
178  //!-------------------------------------------------------------------------
179  //! @brief Send information about Function block over communication link protocol
180  //! @note This method sends information about Function block over specified communication link protocol.
181  //! @param [in] *object_Protocol - Pointer to the communication link protocol
182  //! @return None
183  //! \par Override
184  //! Not allowed
185  //! @attention None
186  //--------------------------------------------------------------------------
187 
188  virtual VOID Send_Information( TProtocol_Base *object_Protocol );
189 
190  //--------------------------------------------------------------------------
191  // Public variables
192  //--------------------------------------------------------------------------
193 
194  // Parameters
195 
197 
198  // Inputs
199 
202 
203  TBlock_Input_Connector object_u16_Inverter_1_Phase_L1_Setpoint; // [-] Output voltage setpoint inverter 1 phase L1
204  TBlock_Input_Connector object_u16_Inverter_1_Phase_L2_Setpoint; // [-] Output voltage setpoint inverter 1 phase L2
205  TBlock_Input_Connector object_u16_Inverter_1_Phase_L3_Setpoint; // [-] Output voltage setpoint inverter 1 phase L3
206 
207  TBlock_Input_Connector object_u16_Inverter_2_Phase_L1_Setpoint; // [V] Output voltage setpoint inverter 2 phase L1
208  TBlock_Input_Connector object_u16_Inverter_2_Phase_L2_Setpoint; // [V] Output voltage setpoint inverter 2 phase L2
209  TBlock_Input_Connector object_u16_Inverter_2_Phase_L3_Setpoint; // [V] Output voltage setpoint inverter 2 phase L3
210 
211  //--------------------------------------------------------------------------
212  // Outputs
213  //--------------------------------------------------------------------------
214 
215  TBlock_Output_Connector object_f32_Sample_Time; // [s] Control event sample time
216 
219 
220  //--------------------------------------------------------------------------
221  // Diagnose outputs
222  //--------------------------------------------------------------------------
223 
224  #ifdef FUNCTIONAL_BLOCK_CREATE_DIAGNOSE_OUTPUTS
225 
226  U16 u16_Control;
227 
228  #endif
229 
230  //----------------------------------------------------------------------------
231  // Protected variables and methods
232  //----------------------------------------------------------------------------
233 
234  protected:
235 
236  //----------------------------------------------------------------------------
237  // Private variables and methods
238  //----------------------------------------------------------------------------
239 
240  private:
241 
242  TPWM_3P2L_Registers *struct_Registers; //!< FPGA mapped registers
243 
244  F32 f32_Clock_Frequency; //!< [Hz] FPGA system clock
245  U16 u16_Periode; //!< [Counts] Periode in counts
246  U16 u16_Half_Periode; //!< [Counts] Half periode in counts
247  U16 u16_Quarter_Periode; //!< [Counts] Quarter periode
248 
249  U16 u16_Inverter_1_Deadtime; //!< Inverter 1 deadtime in FPGA clock counts
250  U16 u16_Inverter_2_Deadtime; //!< Inverter 2 deadtime in FPGA clock counts
251 
252 };
253 
254 //------------------------------------------------------------------------------
255 
256 //! @brief 3-phase 2-level pulse width modulator object class
258 {
259 
260  //----------------------------------------------------------------------------
261  // Public defines, methods and variables
262  //----------------------------------------------------------------------------
263 
264  public:
265 
266  // Register structure for generic access
267  typedef struct
268  {
269 
270  // Control and status registars
271  union
272  {
273  U16 u16_Control; //!< Offset 0x00, Twin PWM module control register
274  U16 u16_Status; //!< Offset 0x00, Twin PWM module status register
275  };
276 
277  // Configuration registers
278  union
279  {
280  U16 u16_Half_Periode; //!< Offset 0x01, Half PWM periode register
281  U16 u16_Status_Latch; //!< Offset 0x01, Status register latch
282  };
283  U16 u16_Dead_Time_Inverter_1; //!< Offset 0x02, Dead time register of the inverter 1
284  U16 u16_Dead_Time_Inverter_2; //!< Offset 0x03, Dead time register of the inverter 2
285 
286  // Inverter 1 PWM setpoint registers
287  I16 i16_Setpoint_Inverter_1_L1; //!< Offset 0x04, Set point of the inverter 1 leg 1
288  I16 i16_Setpoint_Inverter_1_L2; //!< Offset 0x05, Set point of the inverter 1 leg 2
289  I16 i16_Setpoint_Inverter_1_L3; //!< Offset 0x06, Set point of the inverter 1 leg 3
290  U16 u16_Reserve_7; //!< Offset 0x07, Not used
291 
292  // Inverter 2 PWM Setpoint registers
293  I16 i16_Setpoint_Inverter_2_L1; //!< Offset 0x08, Set point of the inverter 2 leg 1
294  I16 i16_Setpoint_Inverter_2_L2; //!< Offset 0x09, Set point of the inverter 2 leg 2
295  I16 i16_Setpoint_Inverter_2_L3; //!< Offset 0x0A, Set point of the inverter 2 leg 3
296  U16 u16_Reserve_B; //!< Offset 0x0B, Not used
297 
298  // Reserved registers
299  U16 u16_Reserve_C; //!< Offset 0x0C, Not used
300  U16 u16_Reserve_D; //!< Offset 0x0D, Not used
301  U16 u16_Reserve_E; //!< Offset 0x0E, Not used
302  U16 u16_Reserve_F; //!< Offset 0x0F, Not used
303 
305 
306  //--------------------------------------------------------------------------
307  // Public methods
308  //--------------------------------------------------------------------------
309 
310  // Constructor and destructor
311  TPWM_3P2L(); //!< Constructor method
312 
313  //!-------------------------------------------------------------------------
314  //! @brief Class destructor method.
315  //! @note None
316  //! \par Override
317  //! Not allowed
318  //! @attention Don't call this method directly.
319  //--------------------------------------------------------------------------
320 
321  virtual ~TPWM_3P2L();
322 
323  //!-------------------------------------------------------------------------
324  //! @brief 3-phase 3-level pulse width modulator memory mapping.
325  //! @note None
326  //! @param [in] struct_Registers_Base_Address Base address within FPGA address space
327  //! @return None
328  //! \par Override
329  //! Not allowed
330  //! @attention None
331  //--------------------------------------------------------------------------
332 
333  VOID Map( TPWM_3P2L_Registers *struct_Registers_Base_Address );
334 
335  //!-------------------------------------------------------------------------
336  //! @brief Function block initialisation method.
337  //! @note None
338  //! \par Override
339  //! Not allowed
340  //! @attention Don't call this method directly.
341  //--------------------------------------------------------------------------
342 
343  virtual VOID Init();
344 
345  //!-------------------------------------------------------------------------
346  //! @brief Function block execution method.
347  //! @note None
348  //! \par Override
349  //! Not allowed
350  //! @attention None
351  //--------------------------------------------------------------------------
352 
353  virtual VOID Execute();
354 
355  //!-------------------------------------------------------------------------
356  //! @brief Send information about Function block over communication link protocol
357  //! @note This method sends information about Function block over specified communication link protocol.
358  //! @param [in] *object_Protocol - Pointer to the communication link protocol
359  //! @return None
360  //! \par Override
361  //! Not allowed
362  //! @attention None
363  //--------------------------------------------------------------------------
364 
365  virtual VOID Send_Information( TProtocol_Base *object_Protocol );
366 
367  //--------------------------------------------------------------------------
368  // Public variables
369  //--------------------------------------------------------------------------
370 
371  // Parameters
372 
374 
375  // Inputs
376 
379 
380  TBlock_Input_Connector object_f32_Inverter_1_Phase_L1_Voltage; // [V] Output voltage inverter 1 phase L1
381  TBlock_Input_Connector object_f32_Inverter_1_Phase_L2_Voltage; // [V] Output voltage inverter 1 phase L2
382  TBlock_Input_Connector object_f32_Inverter_1_Phase_L3_Voltage; // [V] Output voltage inverter 1 phase L3
383 
384  TBlock_Input_Connector object_f32_Inverter_2_Phase_L1_Voltage; // [V] Output voltage inverter 2 phase L1
385  TBlock_Input_Connector object_f32_Inverter_2_Phase_L2_Voltage; // [V] Output voltage inverter 2 phase L2
386  TBlock_Input_Connector object_f32_Inverter_2_Phase_L3_Voltage; // [V] Output voltage inverter 2 phase L3
387 
389 
390  //--------------------------------------------------------------------------
391  // Outputs
392  //--------------------------------------------------------------------------
393 
394  TBlock_Output_Connector object_f32_Sample_Time; // [s] Control event sample time
395 
398 
399  //--------------------------------------------------------------------------
400  // Diagnose outputs
401  //--------------------------------------------------------------------------
402 
403  #ifdef FUNCTIONAL_BLOCK_CREATE_DIAGNOSE_OUTPUTS
404 
405  F32 f32_K;
406 
407  F32 f32_Inverter_1_Phase_L1_Time;
408  F32 f32_Inverter_1_Phase_L2_Time;
409  F32 f32_Inverter_1_Phase_L3_Time;
410 
411  I32 f32_Inverter_2_Phase_L1_Time;
412  I32 f32_Inverter_2_Phase_L2_Time;
413  I32 f32_Inverter_2_Phase_L3_Time;
414 
415  F32 f32_Inverter_1_Minimum_Time;
416  F32 f32_Inverter_1_Maximum_Time;
417 
418  F32 f32_Inverter_2_Minimum_Time;
419  F32 f32_Inverter_2_Maximum_Time;
420 
421  F32 f32_Inverter_1_Offset;
422  F32 f32_Inverter_2_Offset;
423 
424  I32 i32_Inverter_1_Phase_L1_Setpoint;
425  I32 i32_Inverter_1_Phase_L2_Setpoint;
426  I32 i32_Inverter_1_Phase_L3_Setpoint;
427 
428  I32 i32_Inverter_2_Phase_L1_Setpoint;
429  I32 i32_Inverter_2_Phase_L2_Setpoint;
430  I32 i32_Inverter_2_Phase_L3_Setpoint;
431 
432  U16 u16_Control;
433 
434  #endif
435 
436  //----------------------------------------------------------------------------
437  // Protected defines, variables and methods
438  //----------------------------------------------------------------------------
439 
440  protected:
441 
442  //----------------------------------------------------------------------------
443  // Private defines, variables and methods
444  //----------------------------------------------------------------------------
445 
446  private:
447 
448  TPWM_3P2L_Registers *struct_Registers; //!< FPGA mapped registers
449 
450  F32 f32_Clock_Frequency; //!< [Hz] FPGA system clock
451  U16 u16_Periode; //!< [Counts] Periode in counts
452  U16 u16_Half_Periode; //!< [Counts] Half periode in counts
453  U16 u16_Quarter_Periode; //!< [Counts] Quarter periode
454 
455  U16 u16_Inverter_1_Deadtime; //!< Inverter 1 deadtime in FPGA clock counts
456  U16 u16_Inverter_2_Deadtime; //!< Inverter 2 deadtime in FPGA clock counts
457 
458 };
459 
460 //------------------------------------------------------------------------------
461 // End Of File
462 //------------------------------------------------------------------------------
long I32
2s Compliment 32-Bit signed integer datatype defenition
Definition: Defines.h:206
void VOID
Datatypesess datatype definition.
Definition: Defines.h:105
float F32
IEEE-754 32-Bit single presession floating point numbers datatype defenition.
Definition: Defines.h:324
short I16
2s Compliment 16-Bit signed integer datatype defenition
Definition: Defines.h:196
unsigned short U16
Binary 16-Bit unsigned integer datatype defenition.
Definition: Defines.h:193
Function block base class header file.
Function block input connector class.
Definition: Block_Input_Connector.h:83
Function block output connector class.
Definition: Block_Output_Connector.h:59
Function block base class for device.
Definition: Function_Block_Base.h:96
3-phase 2-level pulse width modulator type 1 object class
Definition: PWM_2C3P2L.h:82
TBlock_Input_Connector object_u16_Inverter_2_Phase_L2_Setpoint
Definition: PWM_2C3P2L.h:208
U16 u16_Half_Periode
[Counts] Half periode in counts
Definition: PWM_2C3P2L.h:246
virtual VOID Execute()
Function block execution method.
Definition: PWM_2C3P2L.cpp:189
TPWM_3P2L_T1()
Constructor method.
Definition: PWM_2C3P2L.cpp:68
F32 f32_Clock_Frequency
[Hz] FPGA system clock
Definition: PWM_2C3P2L.h:244
TBlock_Input_Connector object_u16_Inverter_2_Phase_L3_Setpoint
Definition: PWM_2C3P2L.h:209
TBlock_Output_Connector object_bool_Inverter_1_Hardware_Fault
Inverter 1 hardware fault.
Definition: PWM_2C3P2L.h:217
TBlock_Input_Connector object_u16_Inverter_1_Phase_L2_Setpoint
Definition: PWM_2C3P2L.h:204
TBlock_Output_Connector object_f32_Sample_Time
Definition: PWM_2C3P2L.h:215
U16 u16_Inverter_1_Deadtime
Inverter 1 deadtime in FPGA clock counts.
Definition: PWM_2C3P2L.h:249
TBlock_Input_Connector object_bool_Enable_Inverter_1
Definition: PWM_2C3P2L.h:200
TBlock_Input_Connector object_u16_Inverter_2_Phase_L1_Setpoint
Definition: PWM_2C3P2L.h:207
TBlock_Input_Connector object_u16_Inverter_1_Phase_L1_Setpoint
Definition: PWM_2C3P2L.h:203
U16 u16_Inverter_2_Deadtime
Inverter 2 deadtime in FPGA clock counts.
Definition: PWM_2C3P2L.h:250
virtual ~TPWM_3P2L_T1()
Class destructor method.
Definition: PWM_2C3P2L.cpp:118
TPWM_3P2L_Registers * struct_Registers
FPGA mapped registers.
Definition: PWM_2C3P2L.h:242
TBlock_Output_Connector object_bool_Inverter_2_Hardware_Fault
Inverter 2 hardware fault.
Definition: PWM_2C3P2L.h:218
TBlock_Input_Connector object_bool_Enable_Inverter_2
Definition: PWM_2C3P2L.h:201
VOID Map(TPWM_3P2L_Registers *struct_Registers_Base_Address)
3-phase 3-level pulse width modulator memory mapping.
Definition: PWM_2C3P2L.cpp:126
virtual VOID Send_Information(TProtocol_Base *object_Protocol)
Send information about Function block over communication link protocol.
Definition: PWM_2C3P2L.cpp:285
TBlock_Input_Connector object_u16_Inverter_1_Phase_L3_Setpoint
Definition: PWM_2C3P2L.h:205
U16 u16_Quarter_Periode
[Counts] Quarter periode
Definition: PWM_2C3P2L.h:247
U16 u16_Periode
[Counts] Periode in counts
Definition: PWM_2C3P2L.h:245
TBlock_Input_Connector object_f32_Switching_Frequency
Definition: PWM_2C3P2L.h:196
virtual VOID Init()
Function block initialisation method.
Definition: PWM_2C3P2L.cpp:138
3-phase 2-level pulse width modulator object class
Definition: PWM_2C3P2L.h:258
U16 u16_Quarter_Periode
[Counts] Quarter periode
Definition: PWM_2C3P2L.h:453
TBlock_Input_Connector object_bool_Enable_Inverter_1
Definition: PWM_2C3P2L.h:377
U16 u16_Half_Periode
[Counts] Half periode in counts
Definition: PWM_2C3P2L.h:452
TBlock_Input_Connector object_f32_Inverter_2_Phase_L3_Voltage
Definition: PWM_2C3P2L.h:386
TBlock_Output_Connector object_bool_Inverter_1_Hardware_Fault
Inverter 1 hardware fault.
Definition: PWM_2C3P2L.h:396
TBlock_Input_Connector object_f32_Inverter_1_Phase_L3_Voltage
Definition: PWM_2C3P2L.h:382
TBlock_Input_Connector object_bool_Enable_Inverter_2
Definition: PWM_2C3P2L.h:378
F32 f32_Clock_Frequency
[Hz] FPGA system clock
Definition: PWM_2C3P2L.h:450
TPWM_3P2L_Registers * struct_Registers
FPGA mapped registers.
Definition: PWM_2C3P2L.h:448
TBlock_Input_Connector object_f32_Inverter_2_Phase_L2_Voltage
Definition: PWM_2C3P2L.h:385
U16 u16_Inverter_2_Deadtime
Inverter 2 deadtime in FPGA clock counts.
Definition: PWM_2C3P2L.h:456
TBlock_Input_Connector object_f32_DC_Bus_Voltage
Definition: PWM_2C3P2L.h:388
TBlock_Output_Connector object_f32_Sample_Time
Definition: PWM_2C3P2L.h:394
TPWM_3P2L()
Constructor method.
Definition: PWM_2C3P2L.cpp:344
U16 u16_Inverter_1_Deadtime
Inverter 1 deadtime in FPGA clock counts.
Definition: PWM_2C3P2L.h:455
TBlock_Input_Connector object_f32_Inverter_2_Phase_L1_Voltage
Definition: PWM_2C3P2L.h:384
TBlock_Input_Connector object_f32_Inverter_1_Phase_L1_Voltage
Definition: PWM_2C3P2L.h:380
virtual VOID Init()
Function block initialisation method.
Definition: PWM_2C3P2L.cpp:438
U16 u16_Periode
[Counts] Periode in counts
Definition: PWM_2C3P2L.h:451
TBlock_Input_Connector object_f32_Switching_Frequency
Definition: PWM_2C3P2L.h:373
TBlock_Input_Connector object_f32_Inverter_1_Phase_L2_Voltage
Definition: PWM_2C3P2L.h:381
virtual VOID Execute()
Function block execution method.
Definition: PWM_2C3P2L.cpp:489
TBlock_Output_Connector object_bool_Inverter_2_Hardware_Fault
Inverter 2 hardware fault.
Definition: PWM_2C3P2L.h:397
virtual ~TPWM_3P2L()
Class destructor method.
Definition: PWM_2C3P2L.cpp:418
VOID Map(TPWM_3P2L_Registers *struct_Registers_Base_Address)
3-phase 3-level pulse width modulator memory mapping.
Definition: PWM_2C3P2L.cpp:426
virtual VOID Send_Information(TProtocol_Base *object_Protocol)
Send information about Function block over communication link protocol.
Definition: PWM_2C3P2L.cpp:748
Definition: Protocol_Base.h:57
Definition: PWM_2C3P2L.h:268
U16 u16_Dead_Time_Inverter_1
Offset 0x02, Dead time register of the inverter 1.
Definition: PWM_2C3P2L.h:283
U16 u16_Reserve_E
Offset 0x0E, Not used.
Definition: PWM_2C3P2L.h:301
U16 u16_Control
Offset 0x00, Twin PWM module control register.
Definition: PWM_2C3P2L.h:273
U16 u16_Reserve_C
Offset 0x0C, Not used.
Definition: PWM_2C3P2L.h:299
I16 i16_Setpoint_Inverter_2_L3
Offset 0x0A, Set point of the inverter 2 leg 3.
Definition: PWM_2C3P2L.h:295
I16 i16_Setpoint_Inverter_2_L1
Offset 0x08, Set point of the inverter 2 leg 1.
Definition: PWM_2C3P2L.h:293
U16 u16_Half_Periode
Offset 0x01, Half PWM periode register.
Definition: PWM_2C3P2L.h:280
I16 i16_Setpoint_Inverter_1_L3
Offset 0x06, Set point of the inverter 1 leg 3.
Definition: PWM_2C3P2L.h:289
U16 u16_Reserve_F
Offset 0x0F, Not used.
Definition: PWM_2C3P2L.h:302
I16 i16_Setpoint_Inverter_2_L2
Offset 0x09, Set point of the inverter 2 leg 2.
Definition: PWM_2C3P2L.h:294
U16 u16_Status
Offset 0x00, Twin PWM module status register.
Definition: PWM_2C3P2L.h:274
U16 u16_Reserve_7
Offset 0x07, Not used.
Definition: PWM_2C3P2L.h:290
U16 u16_Reserve_B
Offset 0x0B, Not used.
Definition: PWM_2C3P2L.h:296
I16 i16_Setpoint_Inverter_1_L1
Offset 0x04, Set point of the inverter 1 leg 1.
Definition: PWM_2C3P2L.h:287
I16 i16_Setpoint_Inverter_1_L2
Offset 0x05, Set point of the inverter 1 leg 2.
Definition: PWM_2C3P2L.h:288
U16 u16_Status_Latch
Offset 0x01, Status register latch.
Definition: PWM_2C3P2L.h:281
U16 u16_Dead_Time_Inverter_2
Offset 0x03, Dead time register of the inverter 2.
Definition: PWM_2C3P2L.h:284
U16 u16_Reserve_D
Offset 0x0D, Not used.
Definition: PWM_2C3P2L.h:300
Definition: PWM_2C3P2L.h:92
I16 i16_Setpoint_Inverter_1_L3
Offset 0x06, Set point of the inverter 1 leg 3.
Definition: PWM_2C3P2L.h:113
I16 i16_Setpoint_Inverter_2_L3
Offset 0x0A, Set point of the inverter 2 leg 3.
Definition: PWM_2C3P2L.h:119
I16 i16_Setpoint_Inverter_2_L2
Offset 0x09, Set point of the inverter 2 leg 2.
Definition: PWM_2C3P2L.h:118
I16 i16_Setpoint_Inverter_1_L1
Offset 0x04, Set point of the inverter 1 leg 1.
Definition: PWM_2C3P2L.h:111
U16 u16_Half_Periode
Offset 0x01, Half PWM periode register.
Definition: PWM_2C3P2L.h:104
U16 u16_Status
Offset 0x00, Twin PWM module status register.
Definition: PWM_2C3P2L.h:98
U16 u16_Reserve_B
Offset 0x0B, Not used.
Definition: PWM_2C3P2L.h:120
U16 u16_Dead_Time_Inverter_1
Offset 0x02, Dead time register of the inverter 1.
Definition: PWM_2C3P2L.h:107
U16 u16_Reserve_C
Offset 0x0C, Not used.
Definition: PWM_2C3P2L.h:123
U16 u16_Reserve_7
Offset 0x07, Not used.
Definition: PWM_2C3P2L.h:114
U16 u16_Reserve_D
Offset 0x0D, Not used.
Definition: PWM_2C3P2L.h:124
U16 u16_Reserve_E
Offset 0x0E, Not used.
Definition: PWM_2C3P2L.h:125
U16 u16_Reserve_F
Offset 0x0F, Not used.
Definition: PWM_2C3P2L.h:126
U16 u16_Control
Offset 0x00, Twin PWM module control register.
Definition: PWM_2C3P2L.h:97
I16 i16_Setpoint_Inverter_2_L1
Offset 0x08, Set point of the inverter 2 leg 1.
Definition: PWM_2C3P2L.h:117
U16 u16_Dead_Time_Inverter_2
Offset 0x03, Dead time register of the inverter 2.
Definition: PWM_2C3P2L.h:108
U16 u16_Status_Latch
Offset 0x01, Status register latch.
Definition: PWM_2C3P2L.h:105
I16 i16_Setpoint_Inverter_1_L2
Offset 0x05, Set point of the inverter 1 leg 2.
Definition: PWM_2C3P2L.h:112