P013_35_V1_3_CPU.h

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//------------------------------------------------------------------------------
//! @file       P013_35_V1_3_CPU.h
//! @brief      CPU board P013.35 V1.3 hardware driver header file.
//! @attention  No special attention requered.
//! @copyright  (C) 2015-2020 ANVILEX LLC
//!             $HeadURL: https://192.168.3.4:8443/svn/P004_07/ConOpSys/Hardware/P013_35_V1_3_CPU/P013_35_V1_3_CPU.h $
//!             $Revision: 2262 $
//!             $Date: 2020-12-05 07:20:48 +0500 (Sa, 05 Dez 2020) $
//!             $Author: minch $
//------------------------------------------------------------------------------
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
//    this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of ANVILEX nor the names of its contributors may be
//    used to endorse or promote products derived from this software without
//    specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
 
#pragma once
 
//------------------------------------------------------------------------------
// Include system headers
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// Include project headers
//------------------------------------------------------------------------------
 
#include "Target_Base.h"
 
//------------------------------------------------------------------------------
// FPGA base address
//------------------------------------------------------------------------------
  
#define FPGA_BASE (0x60000000)
//#define FPGA_SIZE (0x00010000)
 
//------------------------------------------------------------------------------
// Slot base address definitions
//------------------------------------------------------------------------------
 
//#define FPGA_SLOT_1                 (FPGA_BASE + 0x00000020)
//#define FPGA_SLOT_2                 (FPGA_BASE + 0x00000040)
//#define FPGA_SLOT_3                 (FPGA_BASE + 0x00000060)
//#define FPGA_SLOT_4                 (FPGA_BASE + 0x00000080)
//#define FPGA_SLOT_5                 (FPGA_BASE + 0x000000A0)
//#define FPGA_SLOT_6                 (FPGA_BASE + 0x000000C0)
//#define FPGA_SLOT_7                 (FPGA_BASE + 0x000000E0)
//#define FPGA_SLOT_8                 (FPGA_BASE + 0x00000100)
//#define FPGA_SLOT_9                 (FPGA_BASE + 0x00000120)
//#define FPGA_SLOT_10                (FPGA_BASE + 0x00000140)
 
//#define FPGA_SLOT_11                (FPGA_BASE + 0x00000160)
//#define FPGA_SLOT_12                (FPGA_BASE + 0x00000180)
//#define FPGA_SLOT_13                (FPGA_BASE + 0x000001A0)
//#define FPGA_SLOT_14                (FPGA_BASE + 0x000001C0)
//#define FPGA_SLOT_15                (FPGA_BASE + 0x000001E0)
//#define FPGA_SLOT_16                (FPGA_BASE + 0x00000200)
//#define FPGA_SLOT_17                (FPGA_BASE + 0x00000220)
//#define FPGA_SLOT_18                (FPGA_BASE + 0x00000240)
//#define FPGA_SLOT_19                (FPGA_BASE + 0x00000260)
//#define FPGA_SLOT_20                (FPGA_BASE + 0x00000280)
//#define FPGA_SLOT_21                (FPGA_BASE + 0x000002A0)
//#define FPGA_SLOT_22                (FPGA_BASE + 0x000002C0)
//#define FPGA_SLOT_23                (FPGA_BASE + 0x000002E0)
//#define FPGA_SLOT_24                (FPGA_BASE + 0x00000300)
//#define FPGA_SLOT_25                (FPGA_BASE + 0x00000320)
//#define FPGA_SLOT_26                (FPGA_BASE + 0x00000340)
//#define FPGA_SLOT_27                (FPGA_BASE + 0x00000360)
//#define FPGA_SLOT_28                (FPGA_BASE + 0x00000380)
//#define FPGA_SLOT_29                (FPGA_BASE + 0x000003A0)
//#define FPGA_SLOT_30                (FPGA_BASE + 0x000003C0)
//#define FPGA_SLOT_31                (FPGA_BASE + 0x000003E0)
//#define FPGA_SLOT_32                (FPGA_BASE + 0x00000400)
 
//------------------------------------------------------------------------------
// Internal moduls base address definitions
//------------------------------------------------------------------------------
 
//------------------------------------------------------------------------------
// 
//------------------------------------------------------------------------------
 
class TTarget_P013_35_V1_3_CPU : public TTarget_Base
{
 
  //----------------------------------------------------------------------------
  // Public defines, methods and variables
  //----------------------------------------------------------------------------
  
  public:
 
    // Initialization and finalization methods
    VOID Init(); //!< Initialisation method
    VOID Done(); //!< Finalisation method
  
  // Core clock
  VOID System_Core_Clock_Update();
  U32 Get_SYSCLK_Frequency();
  U32 Get_HCLK_Frequency();
  U32 Get_PCLK1_Frequency();
  U32 Get_PCLK2_Frequency();
  U32 Get_TCLK1_Frequency();
  U32 Get_TCLK2_Frequency();
  U32 Get_IWDG_Frequency();
    
  virtual VOID FPGA_Configure();
 
  virtual U32 Get_CPU_Reset_Source();
  virtual U32 Get_CPU_Device_ID();
  virtual U32 Get_CPU_Revision();
  virtual U32 Get_CPU_Unique_Device_ID( U32 u32_Index );
  virtual U32 Get_CPU_Flash_Size();
  virtual U32 Get_CPU_RAM_Size();
 
  virtual U32 Get_CPU_Stack_Base();
  virtual U32 Get_CPU_Stack_Size();
 
  virtual U32 Get_CPU_Heap_Base();
  virtual U32 Get_CPU_Heap_Size();
 
    // Interrupt management methods
    virtual VOID FPGA_Interrupt_Enable( U32 u32_TickPriority ); //!< Enable interrupt method
    virtual VOID FPGA_Interrupt_Disable(); //!< Disable interrupt method
    
    // Register generic access methods
    virtual VOID FPGA_Write_U16( U16 u16_Address, U16 u16_Value ); //!< Write 16 bit data into FPGA register
    virtual VOID FPGA_Read_U16( U16 u16_Address, U16 *u16_Value ); //!< Read 16 bit data from FPGA register
 
  //----------------------------------------------------------------------------
  // Protected defines, methods and variables
  //----------------------------------------------------------------------------
  
  protected:
 
  //----------------------------------------------------------------------------
  // Private defines, methods and variables
  //----------------------------------------------------------------------------
  
  private:
 
  // System Clock Frequency (Core Clock)
  U32 u32_SYSCLK;
  U32 u32_HCLK;
  U32 u32_PCLK1;
  U32 u32_PCLK2;
  U32 u32_TCLK1;
  U32 u32_TCLK2;
  U32 u32_IWDG;
  
  // Error flag
  U32 u32_Error_Flag;
 
};
 
//------------------------------------------------------------------------------
// Export external references
//------------------------------------------------------------------------------
 
extern void System_Init( void );
 
extern VOID FPGA_Interrupt_Handler();
 
//------------------------------------------------------------------------------
// End Of File 
//------------------------------------------------------------------------------